SHF: Small: Assessing VeSFET Technology for 3-D Integration

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This research takes advantage of the synergy between 3D integration and the Vertical Slit Field Effect Transistor (VeSFET)-based Integrated Circuits (ICs) paradigm. Because further scaling of flat circuits is becoming less profitable, building circuits from vertically stacked multiple active layers seems to be a viable option of delivering continuously improved performance. VeSFET with its unique properties appears to be a uniquely suited transistor to serve as a basis for 3D ICs. It is expected that in terms of heat removal, noise control, power distribution, and testability, VeSFET-based realization of 3D integration will be superior to the traditional 3D CMOS technology. To support this claim, appropriate physical design exploration and thermal management tools will be developed. If successful, the methodologies and techniques developed during the course of this research may have a large impact on the IC manufacturing and designing practices. It is possible that VeSFET-based 3D ICs will delay the necessity of using sophisticated cooling techniques and dark silicon by two to three technology nodes as compared to conventional technologies. It is also likely that this research will result in convincing mainstream chip manufacturers that it is economically viable to produce 3D integrated circuits on the basis of VeSFET. Women and minority students will be encouraged to participate in the research program.