SHF: Small: Assessing VeSFET Technology for 3-D Integration

SHF：小型：评估用于 3D 集成的 VeSFET 技术

• 批准号: 1320401
• 负责人: Malgorzata Marek-Sadowska
• 金额: $ 43.69万
• 依托单位: University of California-Santa Barbara
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2013
• 资助国家: 美国
• 起止时间: 2013-10-01 至 2017-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1320401&HistoricalAwards=false
• 关键词: SHF; Small; Assessing; VeSFET; Technology

This research takes advantage of the synergy between 3D integration and the Vertical Slit Field Effect Transistor (VeSFET)-based Integrated Circuits (ICs) paradigm. Because further scaling of flat circuits is becoming less profitable, building circuits from vertically stacked multiple active layers seems to be a viable option of delivering continuously improved performance. VeSFET with its unique properties appears to be a uniquely suited transistor to serve as a basis for 3D ICs. It is expected that in terms of heat removal, noise control, power distribution, and testability, VeSFET-based realization of 3D integration will be superior to the traditional 3D CMOS technology. To support this claim, appropriate physical design exploration and thermal management tools will be developed. If successful, the methodologies and techniques developed during the course of this research may have a large impact on the IC manufacturing and designing practices. It is possible that VeSFET-based 3D ICs will delay the necessity of using sophisticated cooling techniques and dark silicon by two to three technology nodes as compared to conventional technologies. It is also likely that this research will result in convincing mainstream chip manufacturers that it is economically viable to produce 3D integrated circuits on the basis of VeSFET. Women and minority students will be encouraged to participate in the research program.

这项研究利用了3D集成和基于垂直狭缝场效应晶体管（VeSFET）的集成电路（ic）范例之间的协同作用。由于进一步扩展平面电路的利润越来越少，从垂直堆叠的多个有源层构建电路似乎是提供持续改进性能的可行选择。VeSFET具有独特的特性，似乎是一种独特的晶体管，可以作为3D集成电路的基础。预计在散热、噪声控制、功率分配和可测试性方面，基于vesfet实现的3D集成将优于传统的3D CMOS技术。为了支持这一主张，将开发适当的物理设计探索和热管理工具。如果成功，本研究过程中开发的方法和技术可能对集成电路制造和设计实践产生重大影响。与传统技术相比，基于vesfet的3D集成电路可能会将使用复杂冷却技术和暗硅的必要性推迟两到三个技术节点。这项研究也有可能使主流芯片制造商相信，在VeSFET的基础上生产3D集成电路在经济上是可行的。鼓励女性和少数民族学生参与研究项目。