Architecture, Algorithms, and Circuits for an Energy-Efficient Single-Chip Tera-Op/sec Digital Signal Processor

节能型单芯片万亿次/秒数字信号处理器的体系结构、算法和电路摘要数字信号处理(DSP)工作负载通常是数值密集型、可并行化的，并且在许多应用中要求越来越高。该项目将为能够以高性能和高能效计算DSP工作负载的单芯片处理系统开发体系结构、算法、电路、芯片布局和软件。处理芯片包含大量通过可重新配置的二维网格网络连接的小型异步时钟可编程处理器。这项研究将导致原型处理芯片的设计、制造、测试和表征，包括为少数复杂的多算法应用开发软件。该项目将评估针对这些类型的数字信号处理器工作负载的拟议架构的优点。这项研究可能会在许多应用中带来以前受到最大功耗或吞吐量水平限制的新功能，如延长寿命的医疗设备、大容量消费产品以及非常高吞吐量的雷达和图像处理器。

Architecture, Algorithms, and Circuits for an Energy-Efficient Single-Chip Tera-Op/sec Digital Signal ProcessorAbstractDigital Signal Processing (DSP) workloads are typically numerically intensive, parallelizable, and increasingly required in a number of applications. The project will develop the architecture, algorithms, circuit, chip layout, and software for a single-chip processing system that is capable of calculating DSP workloads with high performance and high energy efficiency. Processing chips contain a very large number of small asynchronously clocked programmable processors connected by a reconfigurable 2-dimensional grid network. The research will result in the design, fabrication, test, and characterization of a prototype processing chip, including the development of software for a small number of complex multi-algorithm applications. The project will evaluate the merits of the proposed architecture for these types of DSP workloads. The research may lead to new capabilities that were previously constrained by maximum levels of power dissipation or throughput, in numerous applications such as life-extending medical devices, high volume consumer products, and very high throughput radar and image processors.