Compiler Optimizations for Network Processors

网络处理器被设计为特定于应用的处理器，以便以非常高的线速执行数据包处理。网络处理器旨在实现更快的处理速度和允许编程的灵活性。实现高处理速度以及提供足够的可编程性导致了网络处理器独特的体系结构设计，其时钟频率非常高，以匹配线路速度。网络处理器的体系结构考虑了分组处理的许多特殊特性，包括多线程、多处理、特殊功能单元、双库寄存器堆、简化的ISA和简化的流水线等。对于编译器来说，生成优化的代码尤其重要，这些代码可以最大限度地利用体系结构功能，而不会给程序员带来沉重的负担。此外，网络处理应用的独特需求(如实时响应需求等)往往会给程序员和编译器编写者增加更多的负担。这可能成为在这些处理器上广泛部署应用程序的障碍。对于入侵分析、服务质量、流量分析等较新的分组处理要求，实际上需要在路由过程中实现越来越多的功能，因此必须消除这些障碍。在这项工作中，建议为英特尔IXP 1200/2400/2800系列开发编译器优化。人们相信，拟议的工作将解决目前构成主要障碍的主要问题：如何在不危及可编程性的情况下将应用程序行为注入优化决策，以及如何执行积极的优化以在高速工作的系统范围内部署这些应用程序。这些优化将在真实系统范围内的真实系统中进行广泛的测试。

Network processors are designed as application specific processors to perform the packet processing at very high line speeds. Network processors are geared towards achieving both fast processing speed and allowing flexibility of programming. Achieving high processing speed as well as providing enough programmability has led to the peculiar architectural design of network processors which is clocked at very high frequencies to match the line speeds. The architecture of network processors considers many special properties for packet processing, including multiple threads, multi-processing, special functional units, dual bank register files, simplified ISA and simplified pipeline, etc. The architectural peculiarities of network processors raise new challenges for compiler design. It is particularly important for the compiler to generate optimized code that could make best use of the architecture features without imposing a heavy burden on the programmer. In addition, unique needs of network processing applications (such as real time response needs etc.) tend to add more burden on the programmers and compiler writers. This could serve as a barrier to the wide scale deployment of applications on these processors. Newer packet processing requirements for intrusion analysis, QoS, traffic analysis etc. in fact demand more and more functionalities to be fulfilled during routing and therefore such barriers must be removed. In this work, it is proposed to develop compiler optimizations for Intel IXP 1200/2400/2800 series. It is believed that the proposed work will solve major problems that pose major barriers currently: how to infuse the application behavior into optimization decisions without jeopardizing the programmability and how to perform aggressive optimizations to deploy these applications in a system wide setting that work at high line speeds. The optimizations will be extensively tested in a real system on real system wide applications.