Improving Memory Power and Performance for Multicore Processors

未来的微处理器将是多核系统，有很大的空间专用于片上高速缓存存储器。多核处理器的潜在性能远远超过传统的单核处理器，但它们的性能受到存储系统无法及时将数据传输到核心的限制。克服这种内存瓶颈问题的传统技术非常耗电，这使得它们不适合未来的功耗限制设计。为了克服内存瓶颈问题，我们正在评估各种各样的多核内存层次设计空间选项，着眼于提高性能和降低功耗。我们正在研究的设计选项包括分层与平铺缓存架构，支持动态平铺分配策略，支持将选择计算移动到数据，支持矢量风格的收集-分散操作，支持选择性更新，功率感知一致性协议和预取机制，以及利用异构线技术的一致性和预取机制。初步结果表明，这些机制将显著提高未来多核处理器的性能并降低功耗。

Future microprocessors will be multicore systems with significant real estate dedicated to on-chip cache memory. The potential performance of multicore processors far exceed that of traditional single-core processors, but their performance is limited by the memory system''s inability to deliver data to cores in a timely fashion. Traditional techniques for overcoming this memory bottleneck problem are power hungry, which makes them unsuitable for future power-limited designs. To overcome the memory bottleneck problem, we are evaluating a wide variety of multicore memory hierarchy design space options, with an eye towards both improving performance and decreasing power. Among the design options we are investigating are hierarchical versus tiled cache architectures, support for dynamic tile allocation policies, support for moving select computation to data, support for vector-style gather-scatter operations, support for selective updates, power-aware coherence protocols and prefetching mechanisms, and coherence and prefetching mechanisms that exploit heterogeneous wire technologies. Preliminary results indicate that these mechanisms will significantly increase performance and reduce power dissipation in future multicore processors.