CSR---SMA: Characterizing, Modeling and Mitigating Soft Error Vulnerability in Multithreaded and Multi-core Execution Environments

未来的微处理器将由数十亿个纳米级晶体管组成，这些晶体管被组织成多核、多线程的微体系结构。由于纳米尺寸的晶体管对外部事件和制造变化很敏感，因此在数十亿个晶体管中的一个中出现一个或多个故障并影响许多线程中的一个的可能性是不可忽略的。较高的数据完整性和可用性要求使得可靠性对计算机的重要性与性能、功耗和产量同等重要。该项目研究系统级组件(即微体系结构、操作系统和程序级别)对软错误的脆弱性进行表征和数学建模的技术。目前的设计方法优化了多核和/或多线程体系结构的性能和能力，但在很大程度上忽略了存在软错误时的可靠性。一项重要而紧迫的研究任务是开发框架、模型和技术来表征和估计软错误的有害影响。这项研究通过1)开发一个统一的、具有可靠性意识的仿真框架来量化由各种不同的硬件和软件组件组成的同时多线程和多核系统的微体系结构软错误脆弱性；以及2)创建快速准确的分析模型来估计和预测硬件和软件组件的软错误脆弱性，而不使用冗长而详细的模拟；能够定量研究软错误脆弱性的框架将使得对新兴的同时多线程和多核体系结构进行具有可靠性意识的设计和研究成为可能。PIS将使用本研究项目的概念、工具、技术和其他结果向研究生和本科生介绍软错误的性质及其对执行环境的影响。这些教学活动将改进有关计算机体系结构、容错计算和纳米计算的课程。在这个项目中开发的工具可以使用PIS实验室开发的设备和中间件在Web上访问和使用。这使得其他学者和工程师在自己的工作中使用它们变得简单明了。

Future microprocessors will consist of billions of nanoscale transistors organized as multi-core multithreaded microarchitectures. Since nano-sized transistors are sensitive to external events and manufacturing variabilities, there is a non-negligible probability of one or more faults occurring in one of billions of transistors and affecting one of many threads. High data-integrity and availability requirements make reliability as important for computers as performance, power consumption, and yield. This project studies techniques for characterizing and mathematically modeling the vulnerability of system-level components (i.e. at the microarchitecture, OS and program levels) to soft-errors.Today's design methodologies optimize the performance and power of multi-core and/or multithreaded architectures, but largely ignore reliability in the presence of soft errors. An important and urgent research task is to develop frameworks, models and techniques to characterize and estimate the deleterious impact of soft errors. This research addresses the above challenge by 1) developing a unified, reliability-aware simulation framework to quantify microarchitecture soft-error vulnerability of simultaneous-multithreading and multi-core systems consisting of a wide range of heterogeneous hardware and software components; and 2) creating fast and accurate analytical models to estimate and forecast soft-error vulnerabilities of hardware and software components without using lengthy and detailed simulations; Frameworks that can quantitatively study soft error vulnerability will enable reliability-aware designs and research for emerging simultaneous-multithreading and multi-core architectures. The PIs will use the concepts, tools, techniques and other results of this research project to introduce graduate and undergraduate students to the nature of soft errors and their impact on execution environments. These teaching activities will lead to improvements in courses on computer architecture, fault-tolerant computing and nanocomputing. The tools developed in this project are accessible and usable over the Web, using equipment and middleware developed by the PIs laboratory. This makes it straightforward for other academics and engineers to use them in their own work.