Parallel-on-Demand --- A Broad Purpose 3D-Integrated Performance Acceleration Layer for General Purpose Processors

随着特征尺寸不断缩小的趋势和工艺技术的进步，在不久的将来，在一个芯片上集成100到1000亿个晶体管是可行的。然而，要实现这一趋势，必须解决一个基本的物理限制，即功耗。功率不再是理想的特性，而是使未来多核处理器系统实用的实际设计约束。另一方面，新兴工艺技术（如3D芯片堆叠）实现了新的集成维度，并为改进带宽、延迟和功耗提供了新的机会。考虑到这些设计限制和新的机会，当前以MIMD方式集成的对称、同构多核处理器将不适合作为可扩展的解决方案，尽管它们减少了实现工作。特别是，对于具有固有的高数据级并行性的应用程序，可以设计利用3D堆叠的新架构。在本研究中，将研究一种新的多核架构，称为并行-按需（POD），以在给定的模具面积和能量预算下开发最大性能。POD没有使用传统的专用ASIC加速器，而是集成了一个性能加速层（PAL），它使用3D芯片堆叠紧密耦合为一个单独的芯片层。PAL利用了从大规模并行处理器中学到的许多思想，但侧重于现代多方面的挑战，如功率和面积效率、片上电线延迟问题、片上互连、与无序内核的集成、向后/向前兼容性、虚拟化资源映射和可扩展性。3d集成性能加速层作为卡扣式功能，使整个系统更加灵活，减少了针对不同目标市场的非重复性工程成本。此外，还将研究新的编程模型，以简化程序员和POD之间的交互、整体硬件复杂性及其随之而来的功率含义。这种3D片上多核架构的成功将为实现具有大量能源效率的高度可扩展计算提供基础，为以最小资源实现Peta-FLOPS计算铺平道路。

With the continuing trend of shrinking feature size and advances in process technology, it would be feasible to integrate 10 to 100 billion transistors on a chip in near future. Nevertheless, one fundamental physical limit, power consumption, must be addressed to enable such trend. Power is no longer a desirable feature but an actual design constraint in making future many-core processor systems practical. On the other hand, emerging process technologies such as 3D die stacking enables a new dimension of integration and provides new opportunities for improving bandwidth, latency, and power. Given such design constraints and new opportunities, the current symmetric, homogeneous multi-core processors integrated in a MIMD manner will be inappropriate as a scalable solution from power- and area-efficiency standpoints despite their reduced implementation effort. In particular, for applications with inherently high data-level parallelism, it is possible to design new architectures that exploit the 3D stacking. In this research, a new many-core architecture, called Parallel-On-Demand (POD), will be investigated to exploit the maximum performance for a given die area and energy budget. Instead of using conventional, special-purpose ASIC accelerators, POD integrates a performance acceleration layer (PAL), which is tightly coupled as a separate die layer using 3D die stacking. PAL leverages many ideas learned from massively parallel processors but focuses on modern multi-faceted challenges such as power and area efficiency, on-chip wire delay issues, on-chip interconnects, integration with out-of-order cores, backward/forward compatibility, virtualized resource mapping, and extensibility. A 3D-integrated performance acceleration layer applied as a snap-on feature also makes the entire system flexible, reducing non-recurring engineering cost for different target markets. Moreover, new programming models will be investigated to simplify the interaction between programmers and POD, overall hardware complexity and its ensuing power implications. The success of such 3D on-die many-core architecture will provide a foundation to enable highly scalable computation with substantial energy efficiency, paving the road to Peta-FLOPS computing with minimal resources.