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SHF: Small: Emerging Memory Architectures for Big Memory Applications

SHF: Small: Emerging Memory Architectures for Big Memory Applications
SHF:小型:适用于大内存应用的新兴内存架构
批准号:
1320074
负责人:
Paul Gratz
金额:
$43.98万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2013
资助国家:
美国
项目状态:
已结题
起止时间:
2013-09-01 至 2017-08-31

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中文摘要
翻译
计算正在发生巨大变化,特别是对Facebook、谷歌和亚马逊等基于云的服务提供商来说。在线服务应用,如社交网络和搜索,对处理器存储系统提出了独特的要求。特别是,这些“大内存”应用程序的工作数据大小比计算机设计研究中通常使用的工作负载大小高出几个数量级。因此,这些应用程序对处理器存储系统施加了不同的压力。与此同时,新的非易失性存储器(NVM)技术,如相变存储器(PCM)、自旋转移扭矩随机存取存储器(STT-RAM)和忆阻器正在涌现,用于替代或增强传统的动态RAM(DRAM)主存储器。这些新的存储器技术承诺更高的容量和更快的访问时间,以及非易失性(断电时数据保留)。因此,它们有可能弥补当前处理器存储器系统在数据容量和速度要求方面的差距,从而产生新的使用模式,如存储类存储器或组合的主存储器和存储实现。这些趋势共同证明了新的存储系统体系结构的必要性,这种体系结构专为大内存应用的挑战而设计,利用新的存储技术和传统的DRAM以及新兴的工艺技术,如3-D芯片堆叠。这项研究将根据未来更大、更接近处理器的非易失性存储器的可用性来表征大内存应用。它将从组织、层次结构和其他结构和管理问题方面研究这些应用程序对新兴内存体系结构的影响。本研究的重点在于:1)利用新兴的技术,如3-D芯片堆叠和新型的、字节可寻址的、高密度的非易失性存储器,为大存储器应用开发存储器体系结构;2)深入研究大存储器应用的指令和数据预取器;3)针对未来使用NVM的大存储器应用,主动管理存储器系统中的性能、功耗和可靠性的高速缓存策略;4)新的存储器转换微体系结构,以满足大存储器应用和存储级主存储器的需求;以及5)服务质量策略,用于根据由DRAM和新的NVM技术组成的未来、混合和复合存储器系统的使用情况来管理存储器布局。这项研究的教育影响将包括培养具有宝贵研究技能的研究生和本科生,同时促进计算机体系结构和分布式系统的最新发展,为技术劳动力做出贡献。
英文摘要
Computing is changing dramatically, particularly for cloud-based service providers such as Facebook, Google, and Amazon. On-line service applications, such as social networking and search, place unique demands on processor memory systems. In particular, these "big-memory" applications have working data sizes several orders of magnitude beyond those found in the workloads typically used in computer design research. As a result, these applications place different stresses on processor memory systems. Simultaneously, new, non-volatile memory (NVM) technologies such as Phase Change Memory (PCM), spin-transfer torque random access memory (STT-RAM), and memristors are emerging for use as a replacement for or augmentation to traditional dynamic RAM (DRAM) main memory. These new memory technologies promise higher capacities and fast access times along with non-volatility (data retention when the power is off). As a result, they have the potential to bridge the gaps in current processor memory systems for both data capacity and speed requirements, leading to new usage models, such as storage class memories or combined main memory and storage implementations. These trends together argue for new memory systems architectures, designed for the challenges of big-memory applications, leveraging new memory technologies together with traditional DRAM and emerging process techniques such as 3-D die stacking. This research will characterize big-memory applications in light of future availability of much larger and nonvolatile memories closer to the processor. It will study the implications of these applications on emerging memory architectures in terms of organization, hierarchies, and other structural and management questions. In particular, this research focuses on the development of the following: 1) Memory architectures for big memory applications, leveraging emerging technologies, such as 3-D die stacking and new, byte-addressable, dense non-volatile memories; 2) Deeply speculating instruction and data prefetchers for big-memory applications; 3) Cache policies that proactively manage performance, power, and reliability in memory systems for future big memory applications utilizing NVM; 4) New memory translation microarchitectures to meet the needs of big-memory applications and storage-class main memories; and 5) Quality-of-service policies to manage memory placement based upon usage in future, hybrid, and composite memory systems composed of DRAM and new NVM technologies. The educational impact of this research will include training graduate and undergraduate students with valuable research skills while advancing the state of the art in computer architecture and distributed systems, contributing to the technology workforce.
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FoMR: Secure, Light-Weight Speculative Engines for Coordinated and Cohesive Speculation in Future Memory Systems
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