SaTC: STARSS: Metric & CAD for DPA Resistance

物理侧通道对嵌入式硬件的安全性构成了很大的威胁。差分功率分析(DPA)攻击是一种众所周知的侧信道威胁，它通过建立统计模型来利用功率与秘密数据或与秘密数据相关的中间值的线性相关性。该项目通过部署由专用门组成的技术单元库来解决DPA漏洞。开发的技术将使嵌入式硬件不太容易受到旁路攻击，从而保护私有用户数据和交易的安全。该项目开发了逻辑级别和网表级别的度量来对电路的DPA漏洞进行建模。对于具有开关概率和开关电容估计的逻辑网络，通过BDDS或其他方法可以有效地计算逻辑电平度量，称为归一化方差。该项目开发了一种更准确但计算成本更高的度量，它是归一化方差的改进，部署在电路级别。

Physical side channels pose a big threat to the security of embedded hardware. The differential power analysis (DPA) attack is a well known side channel threat which exploits the linear dependence of the power on the secret data or an intermediate value correlated to the secret data through statistical model building. This project addresses the DPA vulnerability by deploying a technology cell library consisting of private gates. The technique developed will make embedded hardware less vulnerable to side-channel attacks, thereby securing private user data and transactions.This project develops logic level and netlist level metrics to model the DPA vulnerability of a circuit. The logic level metric, called normalized variance, is efficiently computed for a logic network with switching probability and switched capacitance estimation through BDDs or other methods. The project develops a more accurate but computationally more expensive metric, which is a refinement of the normalized variance and is deployed at circuit level.