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Research Initiation: VLSI Architecture Implementation Transforms

Research Initiation: VLSI Architecture Implementation Transforms
研究启动:VLSI架构实现转变
批准号:
8806169
负责人:
Akhilesh Tyagi
金额:
$7.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
1988
资助国家:
美国
项目状态:
已结题
起止时间:
1988-06-01 至 1990-11-30

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中文摘要
翻译
在超大规模集成电路(VLSI)架构的设计中,设计人员可以对每个子系统的性能参数进行多种选择。设计参数的选择是非常复杂的,很少有整个设计空间的探索。为了探索替代设计,设计师唯一的办法就是彻底重新设计目标部件。Tyagi博士正在研究这一过程的自动化。他正在探索一套通用的设计转换,当将其应用于具有一组性能参数(在面积,能量和时间方面)的给定设计时,可以产生具有期望性能的设计。首席研究员的初步研究表明,这样一组转换可以被识别和实现。他正在将转换应用于设计诸如移位、乘法和排序等功能,并寻找将这些功能组合成具有给定性能特征的体系结构的技术。
英文摘要
In the design of a VLSI architecture, there are several choices of performance parameters for each sub-system available to a designer. The choice of design parameters is so complex that very seldom is the whole design space explored. To explore alternative designs, the only recourse a designer has is to redesign the target parts completely. Dr. Tyagi is investigating automation of this process. He is exploring a general set of design transforms that, when applied to a given design with a set of performance parameters (in terms of area, energy, and time), can produce a design with the desired performance. The principal investigator's initial research indicates that such a set of transforms can be identified and implemented. He is applying the transforms to designing functions such as shifting, multiplication and sorting, and finding techniques to compose these functions into an architecture with given performance characteristics.
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  • 资助金额:
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  • 资助金额:
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  • 批准号:
    0209078
  • 项目类别:
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  • 批准号:
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  • 资助金额:
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  • 负责人:
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海外基金