SHF: Small: Effects of Noise in Ultimate CMOS: Modeling and Simulation Frameworks, Noise-Immune Circuit Designs, and Experimental Validation

随着最近集成电路技术的进步，器件及其工作电压将继续缩小。这种激进的扩展趋势的结果是大幅减少了每个电路节点上的电子总数，使电路更容易受到热噪声的影响，因此有必要采用新的方法来估计这些电路中的噪声行为。此外，对于使用为超低功率应用设计的极低电源电压操作的逻辑电路来说，对由这种噪声引起的误差抑制的需求尤其迫切，在超低功率应用中，由于降低了噪声容限，预计会有更高的错误率。该项目将涉及研究生和本科生，包括代表性不足的群体的成员，从而有助于扩大信息和通信技术领域的劳动力。该项目将通过三个相互关联的推进来解决最终规模的硅基逻辑的抗噪性问题。第一个推力将集中在这些电路中热诱导和电压噪声诱导的错误率的实验验证预测上。第二个推动力涉及开发一个新的模拟框架，用于分析噪声引起的瞬时效应。这一新框架将能够以比传统模拟技术快1到3个数量级的速度捕获罕见的故障诱发事件。基于从这两个初始推进中获得的发现，将开发新的噪声免疫逻辑门结构，从而提供额外的噪声容限。此外，这些结果将被用于设计一种新的综合工具流，它自动确定在哪里以及如何以最佳方式使用这些抗噪声逻辑门，以达到所需的延迟、功率和可靠性要求。

With the recent advances in integrated circuit technology, devices and their operating voltages will continue to shrink. This aggressive scaling trend has the consequence of drastically reducing the total number of electrons on each circuit node, making the circuit much more susceptible to thermal noise making new approaches to estimating noise behavior in these circuits necessary. Also the need for error mitigation resulting from such noise is especially pressing for logic circuits operating using very low supply voltages, designed for ultra-low power applications, where higher error rates are expected due to the reduced noise margins. The project will involve graduate and undergraduate students, include members of underrepresented groups and will thus help enlarge the workforce in information and communication technologies.This project will address the noise immunity of ultimately scaled silicon based logic through three interrelated thrusts. The first thrust will focus on the experimentally validated prediction of thermally induced and voltage-noise induced error rates in these circuits. The second thrust involves development of a new simulation framework for analyzing transient effects due to noise. This new framework will be capable of capturing rare failure-inducing events 1 to 3 orders of magnitude faster than conventional simulation techniques. Based on the findings obtained from these two initial thrusts, new noise-immune logic gate structures that confer additional noise margin will be developed. Moreover, these results will be used to design a new synthesis tool flow, that automatically determines where and how to optimally use these noise-immune logic gates to reach desired delay, power, and reliability requirements.