EAGER: Design and Exploration of Optical Nanoantenna Technology for Advanced IC Testing and Hardware Security

职务名称：EAGER：光学纳米天线：先进的集成电路测试和安全的纳米技术解决方案摘要非技术：今天的集成电路（IC）芯片几乎用于所有的消费电子产品，以及在关键的国防技术和市政支持系统，如电力和供水服务。为了制造这些芯片，使用了最先进的技术，在单个芯片上集成了数十亿个晶体管。目前，我们还没有快速测试这些十亿晶体管芯片的技术诀窍。与此同时，IC芯片的供应链和开发周期也变得越来越分散和全球化。这两个因素，缺乏检测技术和供应链的不确定性，导致了巨大的国家安全风险。敌人将恶意电路（称为硬件木马）插入嵌入关键基础设施组件的IC中以篡改控制和功能的机会从未如此之大。因此，迫切需要为当前和未来技术的光学测试开发全新的解决方案，并确保IC的可靠性。本研究的目的是探索一种全新的模式，使用基于纳米天线的光学技术和相关的测量技术，使快速测试，调试和安全的IC芯片。该项目的预期研究成果包括在纳米级光学，集成电路，成像和模式识别的交叉点，支持快速和可扩展的IC检测的新知识和理解。在教育方面，公共教育机构计划积极招募和支持妇女、代表性不足的少数民族和本科生参加这一项目。本项目将为所有参与本项目的学生提供一个沿着国际合作的多学科培训环境。技术：采用16 nm和14 nm节点的先进IC技术可以在单个芯片上集成数十亿个晶体管，因此需要亚100 nm的光学分辨率来隔离单个晶体管故障。拟议的研究项目旨在探索，评估和优化各种光学纳米天线结构，并开发将纳米天线嵌入单个标准CMOS单元的物理布局和整个CMOS IC芯片的方法。这些纳米天线将被设计成以纳米精度将光激发引导到预定的芯片位置。光学激发与纳米器件的相互作用将得到增强，从而允许测试具有亚衍射限制特征的IC的功能特性。此外，纳米天线将被设计为引起独特的光学散射特征，这些特征对标准细胞几何形状的最小细节高度敏感。因此，通过对标准单元的恶意修改对IC的任何篡改将容易地被检测到。研究人员计划在使用商业CMOS工艺设计的IC芯片中演示这种光学水印技术。拟议的研究将推进光学纳米天线与IC集成的知识，特别是与制造兼容性和设计方法以及它们与周围电路的相互作用有关的知识。成功完成拟议的研究将导致IC芯片测试和安全的范式转变。

Title: EAGER: Optical Nanoantenna: A Nanotechnology Solution for Advanced Integrated Circuit Testing and SecurityAbstractNon-technical: Today's integrated circuit (IC) chips are used in practically all consumer electronics, as well as in critical defense technologies and municipal support systems such as power and water supply services. To build these chips, state-of-the-art technologies are used that integrate billions of transistors on a single chip. Currently, we do not have the technological know-how for rapid testing of these billion-transistor chips. At the same time, the supply chain and development cycle of IC chips have become increasingly fragmented and global. These two factors, lack of inspection technology and uncertainty in the supply chain, have led to an enormous national security risk. The opportunities for enemies to insert malicious circuitry, termed hardware Trojans, into ICs embedded in critical infrastructure components to tamper with the control and functionality have never been greater. Therefore, there is a pressing need to develop radical and novel solutions for optical testing of current and future technologies and ensure the trustworthiness of ICs. The objective of this research is to explore a completely new paradigm using optical technology based on nanoscopic antennas and the associated measurement techniques that would enable rapid testing, debugging, and securing of IC chips. The expected research outcomes of this project include new knowledge and understanding at the intersection of nanoscale optics, integrated circuits, imaging, and pattern recognition that supports rapid and scalable IC inspection. On the educational front, the PIs plan to actively recruit and support women, under-represented minorities and undergraduate students to participate in this project. This project will provide a multi-disciplinary training environment along with international collaboration exposure for all the students involved in this project.Technical: Advanced IC technology using 16 nm and 14 nm nodes can integrate billions of transistors on a single chip, thus requiring sub-100 nm optical resolution for isolation of single transistor faults. The proposed research project aims to explore, evaluate and optimize a variety of optical nanoantenna structures and develop methodologies for embedding nanoantennas into the physical layout of individual standard CMOS cells and into the CMOS IC chip as a whole. These nanoantennas will be engineered to direct optical excitation to predetermined chip locations with nanometer accuracy. The interaction of optical excitation with nanoscale devices will be enhanced allowing for testing functional characteristics of ICs with sub-diffraction limited features. Furthermore, the nanoantennas will be designed to elicit unique optical scattering signatures that are highly sensitive to the smallest details of the standard cell geometry. Thus any tampering of the IC through malicious modification of standard cells would be easily detected. The researchers plan to demonstrate this optical watermarking technology in an IC chip designed using a commercial CMOS process. The proposed research will advance knowledge in the integration of optical nanoantennas with ICs, especially related to fabrication compatibility and design approaches as well as their interaction with surrounding circuitry. A successful completion of the proposed research would lead to a paradigm shift in IC chip testing and security.