PFI:AIR - TT: Memory Processing Unit: A Low Power Processor for Analytics Applications

这个PFI: AIR技术翻译项目的重点是翻译3D芯片堆叠技术，以开发一种新的微处理器架构，称为内存处理单元（MPU）。与目前的解决方案相比，新的架构有望实现更快、更节能的计算。这一点很重要，因为深度学习、大数据分析和数据科学等大量应用都需要强大的处理能力。为了满足这些新应用的需求，性能要求不断增加，而微处理器功率效率的改进速度却在下降（换句话说，摩尔定律预测的趋势开始放缓）。该项目将产生具有完整软件API（应用程序编程接口）的MPU原型芯片设计，用于基于实时语音识别和互联网搜索功能的大数据分析的端到端应用演示。MPU具有以下独特功能：节能的简单核心实现（包括管道组织机制的探索，虚拟内存和一致性），将128个这样的核心连接在一起的实现，通过3D链接连接到内存的核心，以及端到端软件实现。与市场上最先进的服务器芯片相比，MPU架构提供了2到12倍的计算速度，同时将能耗降低了10倍。该项目解决了从研究发现到商业应用的两个技术差距：a)在这种新的高度并发架构上开发端到端软件的困难和所需机制的确定，以及b)对各种应用领域的广泛探索（最初演示语音识别和互联网搜索功能），以定量地确定这种架构相对于最先进的优势。参与该项目的人员，包括研究生和本科生，将通过技术商业化活动、客户访谈和业务发展获得创新和创业经验。此外，该团队还将与威斯康星大学麦迪逊分校的D2P等创业项目合作。

This PFI: AIR Technology Translation project focuses on translating 3D chip-stacking technology to develop a new microprocessor architecture called Memory Processing Unit (MPU). The new architecture offers the promise of faster, more energy efficient calculations than current solutions. This is important because there is a large body of applications such as deep-learning, big-data analytics, and data science that all require significant processing capability. While capability requirements continue to increase to meet the needs of these new applications, the rate of improvement of power efficiency of the microprocessors is decreasing (in other words, the trends predicted by Moore's Law are beginning to slow). This project will result in a prototype chip-design of the MPU with complete software API (Application Programming Interface) for end-to-end application demonstrations based on real-time speech recognition and big-data analytics for Internet search capabilities. The MPU includes the following unique features: an energy-efficient simple core implementation (including exploration of mechanisms for pipeline organization, virtual-memory, and coherence), an implementation that connects 128 such cores together, cores connected through 3D links to memory, and end-to-end software implementation. Compared to state-of-art server chips in the market, the MPU architecture provides two-fold to 12-fold calculation speedup while reducing energy consumption by 10-fold. This project addresses the following two technology gaps as it translates from research discovery toward commercial application: a) the difficulty of developing end-to end software on this new highly concurrent architecture and the determination of the mechanisms required, and b) Extensive exploration of various application domains (initially demonstrating speech recognition and internet search capabilities) to determine quantitatively the benefits of this architecture over the state-of-the-art. Personnel involved in this project, including graduate students and undergraduates, will receive innovation and entrepreneurship experiences through the technology commercialization activities, customer interviews, and business development. In addition the team will work with entrepreneurship programs like D2P at UW-Madison.