CRII: SaTC: Robust Design-for-Security (DFS) Architecture for Enabling Trust in Integrated Circuits (IC) Manufacturing and Test

由于半导体制造成本过高，大多数计算机芯片设计公司将其生产外包给离岸代工厂。由于这些芯片中的许多可能是在有限信任的环境中制造的，因此近年来出现了知识产权（IP）盗版和集成电路（IC）生产过剩的问题。本项目的重点是设计一个安全的逻辑锁定技术，使不受信任的IC制造的保护。开发的解决方案可以抵抗所有已知的攻击。逻辑锁定是一种很有前途的解决方案，可以在外包IC制造中实现信任，其中通过修改功能来混淆设计。一个被锁定的芯片将产生不正确的结果，除非被混淆密钥激活。然而，基于布尔可满足性（SAT）的算法已被证明可以有效地确定混淆密钥并打破锁定机制。在这项工作中，一种新的安全单元（SC）的设计，防止混淆密钥被捕获在芯片的内部触发器和功能模式后禁用扫描转储。SC提供了一个完整的保护，防止基于SAT和其他现有的攻击，利用扫描数据。此外，SC还支持商业工具在没有混淆密钥的情况下生成测试模式。这将有助于在芯片激活前进行制造测试，从而防止IC生产过剩。拟议的研究将通过努力支持半导体制造和测试过程中的信任来满足行业和政府的关键需求。教育和研究的结合是该项目的一个关键目标。这项研究是多学科的，连接集成电路设计，仿真和测试，硬件安全和嵌入式系统的领域。从事该项目的研究生和本科生将接受电气和计算机工程各个领域的跨学科培训。为研究生和本科生开设的一门关于硬件安全的新的高年级课程将为政府和商业部门创造下一代网络安全人才。预期作为本项目成果的工件将在执行期间和之后公开访问。所有同行评审的出版物都可通过链接http://www.eng.auburn.edu/~uguin/publications.html访问。复制结果所需的所有原始输入数据、衍生数据和代码版本将与文章的源代码一起存储，以便第三方可以复制结果。所有出版物都将保持这一做法。如果数据量很大，将提供一种安全的替代共享方式。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

Due to the prohibitive costs of semiconductor manufacturing, most computer chip design companies outsource their production to offshore foundries. As many of these chips may be manufactured in environments of limited trust, problems of the piracy of intellectual property (IP) and the overproduction of integrated circuits (ICs) have emerged in recent years. This project focuses on designing a secure logic locking technique to enable protection against untrusted IC manufacturing. The developed solution is resistant to all known attacks. Logic locking is a promising solution for enabling trust in outsourced IC manufacturing, where a design is obfuscated by modifying the functionality. A locked chip will produce incorrect results unless activated by an obfuscation key. However, Boolean satisfiability (SAT)-based algorithms have been shown to effectively determine the obfuscation key and break the locking mechanisms. In this work, a novel secure cell (SC) is designed, which prevents the obfuscation key from being captured in internal flip-flops of a chip and disables scan dump after functional mode. The SC provides a complete protection against SAT-based and other existing attacks that utilize scan data. In addition, SC provides support for commercial tools to generate test patterns without having the obfuscation key. This will help perform the manufacturing test before the activation of chips, and thus preventing IC overproduction. The proposed research will serve a critical need for the industry and government by working to support trust in the semiconductor manufacturing and test process. The integration of education and research is a key objective of this project. This research is multidisciplinary, linking the fields of IC design, simulation and test, hardware security, and embedded systems. The graduate and undergraduate students working on this project will receive interdisciplinary training across diverse areas of electrical and computer engineering. A novel upper-division course on hardware security for the graduate and undergraduate students will create a next-generation cybersecurity workforce for the government and commercial sectors. The artifacts expected as outcomes from this project will be publicly accessible during the period of performance and afterwards. All peer-reviewed publications will be accessible through the link http://www.eng.auburn.edu/~uguin/publications.html. All raw input data, derived data and code versions needed for reproduction of results will be stored with the sources for the articles, so that third parties can reproduce the results. This will be maintained for all publications. If the data are large, a secure alternative means for sharing will be provided.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.