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SHF: EAGER: Toward Energy-Efficient Heterogeneous Computing Integrating Polymorphic Magnetic and CMOS Devices

SHF: EAGER: Toward Energy-Efficient Heterogeneous Computing Integrating Polymorphic Magnetic and CMOS Devices
SHF:EAGER:迈向集成多态磁性和 CMOS 器件的节能异构计算
批准号:
2021230
负责人:
Shaloo Rakheja
金额:
$29.94万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2019
资助国家:
美国
项目状态:
已结题
起止时间:
2019-09-15 至 2023-06-30

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中文摘要
翻译
非传统材料和器件与硅互补金属氧化物半导体(CMOS)技术的集成可以实现具有与面积、能效和弹性相关的潜在益处的新型计算平台。在这方面,在磁性设备中存储和操纵信息是有前途的。这是因为,与CMOS器件不同,磁性器件中的信息可以在没有任何能量耗散的情况下存储,而能量仅用于读取或写入信息。磁性器件的这种低功率操作对于具有低操作功率要求的物联网和智能感测等应用非常有利。这项研究将把这种磁性器件的物理特性与它们在电路中的使用联系起来,在电路中磁性器件与硅器件共存并互补,以增强功能和用户体验。这项研究的结果将被纳入纽约大学(NYU)每年举办的动手电路设计研讨会。具体来说,学生将在桌面实验和交互式在线学习工具中学习磁铁的物理学。该项目还将开发有关磁存储器的内容,这些内容将在纽约大学每年教授的纳米电子器件和电路课程中介绍。该项目还将通过普渡大学托管的科学和工程网关(称为nanoHUB)公开发布该研究中生成的设备模型和模拟数据,以使相关领域的研究人员和教育工作者受益。虽然存在其他可能性,但该特定项目将专注于两种特定的磁性设备,即压控拓扑自旋开关(vTOPSS)和磁电自旋轨道(MESO)器件。这些磁性设备提供了10至100倍的上级能源效率的二进制操作相比,他们的磁性同行。这些器件的另一个独特之处在于,它们的逻辑功能可以在制造后进行配置,这在电路和系统层面上转化为弹性以及面积和功率优势。将针对大规模蒙特-卡罗模拟开发并校准vTOPSS和MESO设备的延迟、能量耗散、热稳定性和错误率的基于物理的模型。潜在的互连,包括金属和半导体纳米线,对器件性能的影响将被量化。器件级模型将被用来开发一个标准的单元库的布尔逻辑门与vTOPSS和MESO作为开关元件。该单元库将能够量化磁性CMOS计算平台的性能指标。本研究采用的物理电路方法将推动电路设计中的创新概念,从而最大限度地提高拟议技术的竞争力。该奖项反映了NSF的法定使命,并通过使用基金会的知识价值和更广泛的影响审查标准进行评估,被认为值得支持。
英文摘要
The integration of non-conventional materials and devices with silicon Complementary Metal Oxide Semiconductor (CMOS) technology can enable a new type of computing platform with potential benefits related to area, energy efficiency, and resiliency. In this regard, storing and manipulating information in magnetic devices is promising. This is because, unlike CMOS devices, information in magnetic devices can be stored without any energy dissipation, while energy is needed only to read or write information. This low-power operation of magnetic devices is highly advantageous for applications such as Internet of Things and intelligent sensing that have low operating power requirements. This research will connect the physics of such magnetic devices with their use in circuits in which magnetic devices co-exist with and complement silicon devices for enhanced functionality and user experience. Results from this research will be incorporated into a hands-on circuit design workshop organized annually at New York University (NYU). Specifically, students will learn about the physics of magnets in table top experiments and interactive online learning tools. The project will also develop content on magnetic memory that will be introduced in a course on nanoelectronics devices and circuits taught annually at NYU. The project will also publicly release the device models and simulation data generated in this research via the science and engineering gateway hosted at Purdue University, known as the nanoHUB, to benefit researchers and educators working in related fields.While other possibilities exist, this particular project will focus on two specific magnetic devices, namely the voltage-controlled topological-spin switch (vTOPSS) and the magneto-electric spin-orbit (MESO) device. These magnetic devices offer 10 to 100 times superior energy efficiency for binary operations compared to their magnetic counterparts. Another unique feature of these devices is that their logic functionality can be configured post-fabrication, which translates into resilience and area- and power benefits at the circuit and system level. Physics-based models of the latency, energy dissipation, thermal stability, and error-rate of vTOPSS and MESO device will be developed and calibrated against large-scale Monte-Carlo simulations. Impact of potential interconnects, including metallic and semiconducting nanowires, on device performance will be quantified. Device-level models will be used to develop a standard cell library of Boolean logic gates with vTOPSS and MESO as the switching elements. The cell library will enable the quantification of performance metrics of magnetic-CMOS computing platform at scale. The physics-to-circuits approach adopted in this research will drive innovative concepts in circuit design that can maximize the competitiveness of the proposed technology.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
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CAREER: A multi-scale and hierarchical computational framework to model III-nitride devices operating in the near-terahertz regime
IUCRC Phase I: University of Illinois at Urbana-Champaign (UIUC): Center for Advanced Semiconductor Chips with Accelerated Performance (ASAP)
2022 Device Research Conference
  • 批准号:
    2227544
  • 项目类别:
    Standard Grant
  • 资助金额:
    $1.0万
  • 财政年份:
    2022
  • 负责人:
    Shaloo Rakheja
  • 依托单位:
79th Device Research Conference. To Be Held Virtually June 20-23, 2021.
  • 批准号:
    2133323
  • 项目类别:
    Standard Grant
  • 资助金额:
    $1.0万
  • 财政年份:
    2021
  • 负责人:
    Shaloo Rakheja
  • 依托单位:
海外基金