Highly Efficient CMOS Transmitter for Emerging Broadband Wireless Communication Systems

移动的计算和无线互联网的最近发展已经导致对配备有以多标准能力操作的无线局域网的便携式计算机和智能电话的需求增加。由于半导体技术的进步，允许在单个互补金属氧化物半导体（CMOS）芯片上安装更多的器件，在不久的将来，局域无线网络中将包含更多的标准和应用。无线连接已经远远超出了智能手机和人对人通信，现在包括意想不到的设备到设备通信系统。朝向更快和更有效的通信系统的趋势要求通过采用更先进的编码方案来最佳地使用可用频谱，该编码方案增加每个符号的传输比特数，并且导致每个可用带宽的信息的更有效传输。但是，这些系统需要严格的发射机/接收机（TX/RX）规范。先进的编码方案为每个发送符号分配更多的比特，然后符号之间的电压差减小，使得通信方案对背景噪声更敏感，然后它要求上级的信号功率与噪声功率比。信号功率通常是有限制的，以允许其他用户共享可用的频谱;对于手持设备，必须优化功率的使用以延长电池的充电时间。主要的挑战是晶体管的线性度无法满足先进标准的要求。设备非线性产生发射和接收信号的非线性副本，其中多个互调产物落在信号频带中，这降低了原始信号的质量。该研究计划将为解决这些问题的变送器开发创新的基于数字CMOS的全球校准方案。到2025年，联网智能设备的预测市场将超过750亿台设备。然而，新兴的多媒体应用要求更多的带宽和更好的系统性能，由于使用频谱有效的调制方案与大的峰均比。超宽带收发器对传输误差的容忍度较低，并要求严格的收发器线性度、整个信号带宽内的平坦增益和线性相位响应。此外，功率放大器（PA）是负责在手持设备的大部分功耗，提高功率效率和性能的发射机是至关重要的移动的通信系统的进步。发射机优化是一项复杂的任务，无法通过使用传统的校准方法来实现。发射机的误差大多是非线性的和信号相关的，因此这些误差的评估是一项困难的任务。典型的补偿方法在功耗和数字资源方面是复杂和昂贵的，并且在宽带应用中使用它们是非常困难的。情感成本是另一个重要的制约因素。目前，超过85%的现有发射机是用非CMOS技术制造的，而控制和信号处理是用CMOS技术实现的。全CMOS收发器提供片上系统解决方案将对收发器的效率、可靠性和生产成本产生重大影响。所提出的CMOS TX架构利用基于创新的电流按需电流导引数模转换器的敏捷包络跟踪系统，该电流导引数模转换器增强了电源管理系统的跟踪能力和电源效率。此外，所提出的宽带低功耗数字线性化技术考虑PA非线性、带宽和相位TX限制以及记忆效应。建议的发射机架构将实现一个误差矢量幅度低于-40分贝和功率增加效率超过30%时，处理400 MHz的信号带宽。这一奖项反映了NSF的法定使命，并已被认为是值得通过评估使用基金会的智力价值和更广泛的影响审查标准的支持。

Recent developments in mobile computing and wireless internet have led to an increasing demand for portable computers and smart phones equipped with wireless local area networks operating with multi-standard capabilities. More standards and applications will be incorporated in the near future local area wireless networks due to the advances of the semiconductors technology that allows more devices on a single complementary metal-oxide-semiconductor (CMOS) chip. The wireless connectivity has expanded far beyond smartphones and person-to-person communications to now encompass unexpected device-to-device communication systems. The trend towards faster and more efficient communication systems demand an optimal use of the available spectrum by employing more advanced coding schemes that increases the number of transmitted bits per symbol, and that results in more effective transmission of information per available bandwidth. But, these systems demand stringent transmitter/receiver (TX/RX) specifications. The advanced coding schemes assign more bits per transmit symbol, then the voltage difference between symbols reduces making the communication scheme more sensitive to the background noise, then it demands superior signal power to noise power ratio. The signal power is usually bounded to allow other users to share the available spectrum; for handheld devices it is a must to optimize the use of power to extend battery’s recharging time. The major challenge is the lack of transistor’s linearity to satisfy the requirements of advanced standards. The device non-linearities generate non-linear replicas of the transmitted and received signals with multiple intermodulation products falling in the signal band which degrade the quality of the original signal. This research program will develop innovative digital CMOS based global calibration schemes for the transmitter that addresses these issues.The predicted market for connected smart devices will be over 75 billion devices by 2025. However, the emerging multimedia applications demand more bandwidth and better system performance due to the use of spectral efficient modulation schemes with large peak-to-average ratios. The ultra-broadband transceivers are less tolerant to transmit errors and demand stringent transceiver linearity, flat gain in the entire signal bandwidth and linear phase response. In addition, the power amplifier (PA) is responsible for most of the power consumption in hand-held devices; improving the power efficiency and performance of the transmitter is critical for the advance of mobile communication systems. The transmitter optimization is a complex task that cannot be achieved by using conventional calibration methodologies. Most of the transmitter errors are non-linear and signal dependent, then the evaluation of these errors is a difficult task. The typical compensation methodologies are complex and expensive in terms of power consumption and digital resources, and it is very difficult to use them in broadband applications. Affective cost is another important constraint. Currently, over 85% of the existing transmitters are fabricated in non-CMOS technologies, while the control and signal processing is implemented in CMOS technologies. Full CMOS transceivers offer a system solution on chip will have significant impact on the efficiency, reliability, and production cost of the transceivers. The proposed CMOS TX architecture leverages on an agile envelope tracking system based on an innovative current on demand current-steering digital-to-analog converter that enhances the tracking capabilities and power efficiency of the power management system. Also, the proposed broadband low-power digital linearization technique accounts for PA non-linearities, bandwidth and phase TX limitations, as well as memory effects. The proposed TX architecture will achieve an error vector magnitude under -40dB and power added efficiency over 30% when handling 400MHz signal bandwidth.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.