REDOX: Decrease of simulation- and radiation-time of rad-hard circuits by optimizing of SET models

正在运行的REDOX项目的主要目标是建立一个统一的框架，用于在电路级优化和准确表征单粒子瞬态（SET）效应。这将有助于减少对大量器件模拟和辐照实验的需求，并促进新型抗辐射CMOS和BiCMOS库的有效开发。为了实现这一目标，需要更好地理解所有相关的辐照、设计、技术和操作参数对组合逻辑中SET产生和传播的影响，以及SET进入时序逻辑的锁存。在批准的项目的第一部分中，我们研究了标准和非标准逻辑门中的SET效应，采用SPICE模拟250，130和65 nm CMOS技术，以及250 nm技术的TCAD模拟。第一阶段的主要成果是建立了两个分析模型，用于预测标准和非标准逻辑门的SET鲁棒性。此外，我们已经获得了实质性的洞察SET效应的物理机制和照射，设计和操作参数对SET电流和电压脉冲的形成的影响。此外，我们已经进行了详细的分析，先进的技术进行实验表征的SET效应，和第一个测试芯片的SET脉冲宽度测量已经设计和制造在IHP的250 nm体CMOS工艺。根据该项目头18个月取得的成果，我们有几份文件，我们认为，请求延长该项目将使最初提出的目标得以充分实现。为了实现所提出的目标，计划的研究将集中在：（1）进一步改进在项目第一阶段得出的SET鲁棒性模型，（2）使用所获得的关于SET效应的知识来增强现有的SET电流，SET电压和SET传播模型，以及（3）将改进的SET模型集成到一个连贯的SET评估框架中。SET模型和完整的表征框架将使用SPICE模拟和辐照实验在选定的基准电路上进行测试。此外，关于目前的最新技术水平，我们想稍微扩大我们的工作范围，处理项目第一版中没有处理的其他重要问题。

The main goal of the running REDOX project is to establish a unified framework for optimized and accurate characterization of Single Event Transient (SET) effects at the circuit level. This will help in reducing the need for extensive device simulations and irradiation experiments, and facilitate the effective development of novel rad-hard CMOS and BiCMOS libraries. To accomplish this goal, it is required to better understand the impact of all relevant irradiation, design, technological and operating parameters on the SET generation and propagation within the combinational logic, and its latching into the sequential logic.In the approved first part of the project we have investigated the SET effects in standard and non-standard logic gates, employing SPICE simulations for 250, 130 and 65 nm CMOS technologies, and TCAD simulations for 250 nm technology. The main achievement in the first phase is the establishment of two analytical models for predicting the SET robustness of standard and non-standard logic gates. In addition, we have gained substantial insight into the physical mechanisms of SET effects and the impact of irradiation, design and operating parameters on the formation of SET current and voltage pulses. Also, we have conducted detailed analysis of advanced techniques for experimental characterization of SET effects, and a first test chip for SET pulse width measurement has been designed and manufactured in IHP’s 250 nm bulk CMOS process. Based on the results achieved in the first 18 months of the project, we have several papers.We believe that the requested extension of the project would allow for a full accomplishment of the originally proposed objectives. To achieve the proposed objectives, the planned research will be focused on: (1) further improvement of the SET robustness models derived in the first phase of the project, (2) use of the acquired knowledge on SET effects to enhance existing SET current, SET voltage and SET propagation models, and (3) integration of the improved SET models into a coherent SET evaluation framework. The SET models and the complete characterization framework will be tested on selected benchmark circuits using SPICE simulations and irradiation experiments. In addition, with respect to the current state-of-the-art, we would like to slightly extend the scope of our work by addressing additional important issues which have not been addressed in the first version of the project.