PARFAIT II: Power-aware AmbipolaR Fpga ArchITecture II

在PARFIT II中，人们正在研究具有p-和n-电导率可调节的平面可重构场效应晶体管(RFET)。虽然Parfait I主要通过模拟探索了这些双极晶体管的技术基础，但Parfait II的重点是晶体管的制造、逻辑门的开发及其在复杂电路中的使用。为此，必须设计一种可靠和可重复的平面RFET制造工艺，并且必须回答有关肖特基接触的稳定性和RFET的电对称性的问题。在联合规范阶段之后，将通过设计、制造和测量测试电路来验证来自Parfait I的模拟模型并使其适应实际制造条件。其目的是开发一种高效的紧凑模型，既能反映动态可重构性，又能考虑寄生效应，并允许较短的仿真时间。为能够在实际应用中使用具有更大规模的几何尺寸的可重构晶体管奠定了基础。此外，Parfait II将研究电路和系统级的应用，其中所探索的RFET的模拟和测量特性是最有希望的。除了动态改变逻辑门的开关功能外，这些主要是节省空间的存储器中逻辑单元的实现以及在模拟电路(例如BPSK调制器)中的使用。该项目的一个主要部分是从工艺到系统层面对RFET的温度行为进行研究：由于RFET的制造不使用掺杂，显然RFET可以在比传统CMOS电路更宽的温度范围内工作。由于纯模拟在这里不能提供可靠的结果，所以Parfait II将在70K到200K的范围内进行测量，如果结果是肯定的，则将测量范围扩大到4K。如果电路工作在如此宽的温度范围内，各种效应可能会影响信号的传播时间。因此，对这些影响的动态补偿将在电路和系统级进行研究，特别是对于基于RFET的FPGA体系结构：利用FPGA电路的可重构性来动态地重新配置部分FPGA来测量信号传播时间。根据测量，平面RFET的能力被用来通过附加的后门以细粒度的方式调整单元的阈值电压、漏电流和开关电流，而与配置的逻辑功能(通过前门设置)无关。这种方法旨在补偿温度和工艺的影响，特别是在极端操作环境下。

In PARFAIT II, planar reconfigurable field-effect transistors (RFETs) with electrically adjustable p- and n-conductivity are being researched. While PARFAIT I explored the technological fundamentals of these ambipolar transistors largely by simulation, the focus of PARFAIT II is on the fabrication of the transistors, the development of logic gates and their use in complex circuits. For this purpose, a reliable and reproducible fabrication process for planar RFETs has to be designed and questions regarding the stabilization of the Schottky contacts and electrical symmetry of the RFET have to be answered. Following a joint specification phase, the simulative models from PARFAIT I will be verified and adapted to real manufacturing conditions by designing, manufacturing and measuring test circuits. The aim is to develop an efficient compact model that reflects the dynamic reconfigurability, incorporates parasitic effects and still allows short simulation times. The foundations will be laid to be able to use reconfigurable transistors in real applications with scaled geometries on a larger scale.Further, PARFAIT II will investigate circuit- and system-level applications for which the simulated and measured characteristics of the RFETs explored are most promising. In addition to dynamically changing the switching function of logic gates, these are primarily the space-saving realization of logic-in-memory cells and the use in analog circuits (e.g. BPSK modulators). A major part of the project is the investigation of the temperature behavior of the RFET from the technology to the system level: Since no doping is used for the fabrication of RFETs, it is obvious that RFETs can be operated in wider temperature ranges than conventional CMOS circuits. Since pure simulations do not provide reliable results here, PARFAIT II will perform measurements in the range of 70K to 200K and extend them down to 4K if the results are positive. If circuits are operated over such wide temperature ranges, various effects can be expected to influence the signal propagation times. Therefore, a dynamic compensation of these effects will be investigated on circuit and system level, especially for an FPGA architecture based on RFETs: The reconfigurability of the FPGA circuit will be used to dynamically reconfigure parts of the FPGA for measuring the signal propagation times. According to the measurements, the capability of the planar RFETs is used to adapt threshold voltages, leakage currents and switching currents of cells in a fine-granular way via the additional back gate, independent of the configured logic function (set via the front gates). This approach is intended to compensate for temperature and process influences, especially with regard to extreme operating environments.