Technology-aware Asymmetric 3D-Inteconnect Architectures: Templates and Design Methods

新的生产方法使异质3D系统芯片(3D-SoC)的设计成为可能，3D-SoC由采用不同技术制造的堆叠硅芯片组成。与同类SoC相比，这允许调整每个芯片的工艺特性，以满足放置在每个层中的组件的特定要求。异类3D-SoC为嵌入式和高性能系统提供了前所未有的集成可能性。为了开发这一潜力，需要强大、灵活和可扩展的通信基础设施。然而，目前的互连体系结构(IAS)默认假设为多层同质3D-SoC，并且没有考虑不同工艺参数对互连体系结构拓扑、体系结构和微体系结构层次的影响。我们的目标是两个主要的创新：首先，我们将开发异质3D-SoC中单个芯片层的特定技术特征。因此，我们将重新评估和扩展针对异类和混合2D互连体系结构的现有方法。其次，我们的目标是发现新的组件之间的相互作用机制，这些组件甚至可以在微体系结构层面上分布在空间上，以利用它们在不同技术中制造的不同特征。这些方面的结合导致了技术不对称3D-互连体系结构(TA-3D-IAS)，正如本提案首次定义的那样。该项目的主要成果将是对TA-3D-IAS作为异质3D-SoC的一部分有更深入的理解。此外，我们将为TA-3D-IAS的设计制定系统的设计方法和一套架构模板。为此，我们将创建一个全面的仿真框架，用于分析TA-3D-IAS的设计空间，该框架将能够考虑通信基础设施的所有组件的特定技术参数。此外，我们将提供参考基准和选定的TA-3D-IAS，这将允许其他研究团队评估和比较他们的想法。

New production methods enable the design of heterogeneous 3D-System-on-Chips (3D-SoCs), which consist of stacked silicon dies manufactured with different technologies. In contrast to homogeneous SoCs, this allows to adjust the technological characteristics of each die to the specific requirements of the components placed in each layer. Heterogeneous 3D-SoCs provide unprecedented integration possibilities for embedded and high performance systems. To exploit that potential, powerful, flexible, and scalable communication infrastructures are required. Yet, current interconnect architectures (IAs) tacitly assume a multilayer homogeneous 3D-SoC and do not consider the influence of different technology parameters on the topology, architectural, and micro-architectural level of the IA.In this project, we aim to develop architectural templates and design methods for 3D-interconnect architectures for heterogeneous 3D-SoCs. We target two main innovations: First, we will exploit the specific technology characteristics of individual chip layers in heterogeneous 3D-SoCs. Therefore, we will re-evaluate and extend existing approaches for heterogeneous and hybrid 2D-interconnect architectures. Second, we aim at discovering new interaction mechanisms among components, which may be spatially distributed even at the micro-architectural level, to exploit their diverse features when manufactured in different technologies. The combination of these aspects leads to technology asymmetric 3D-interconnect architectures (TA-3D-IAs), as defined in this proposal for the first time.The main outcome of the project will be a deeper understanding of TA-3D-IAs as part of heterogeneous 3D-SoCs. Further, we will develop systematic design methodologies and a set of architectural templates for the design of TA-3D-IAs. Therefor we will create a full-fledged simulation framework for the analysis of TA-3D-IAs' design space, which will be capable of accounting for technology-specific parameters for all components of the communication infrastructure. In addition, we will provide reference benchmarks and selected TA-3D-IAs, which will allow other research teams to evaluate and compare their ideas.