Performance Improvement by Exploiting Instruction-Level Parallelism

这项研究的目的是开发指令级并行性，并研究超标量体系结构的各种性能改进技术。主要研究成果如下：L。超标量处理器的基本控制机制提出了提高超标量处理器性能的各种技术，并通过软件仿真验证了其有效性。这些技术包括：(1)具有有序发布和无序执行策略的四指令多路复用流水线方案。该方案不仅实现了高速执行，而且大大降低了硬件成本。(2)强大的分支预测机制，将分支目标缓冲区和静态分支预测方法相结合。与早期的分支机构解决方案一起，为预防控制灾害做出了巨大贡献。(3)避免不精确中断的新机制；(4)针对读/存危险的静态解析方法。优化编译器优化编译器对于提高超标量处理器的性能至关重要。研究了一种软件流水线方案、一种循环展开方案以及这些方案的强大组合，并通过仿真验证了它们的有效性。最多可以获得5倍的性能提升。

The purpose of this research is to exploit parallelism at instruction level and to investigate various performance improvement techniques for superscalar architecture. Main results of the research are the following :l. Basic control mechanism for superscalar processorVarious techniques for improving the performance are proposed and verified to be effective by software simulation. These techniques include ; (1) Four-instruction-multiplexed pipelining scheme with in-order issue and out-of-order execution strategy. This scheme not only attains high-speed execution but also reduces hardware cost drastically. (2) Powerful branch prediction mechanism in which the branch target buffer and static branch prediction methods are combined. Together with the early branch resolution, this gives a great contribution to preventing control hazards. (3) New mechanism to escape imprecise interruption, (4) Static resolution method against load/store hazards.2. Optimizing compilerOptimizing compiler plays an essential role in improving the performance of superscalar processor. A software pipeline scheme, a loop-unrolling scheme and a powerful combination of these schemess are investigated and verified to be effective by simulation. Maximally 5 times higher performance can be gained.