Research on Single Electron Tunnel Device using substrates with small misorientations

(1)利用具有小取向偏差的Si（100）衬底在超高真空条件下退火，以高可控性实现了单原子层或双原子层台阶的形成。通过电流加热样品，得到Si（100）衬底向（110）方向的错取向角为4和1。(2)采用具有相同取向的表面群包围的小岛设计和制造单电子晶体管。提出了有利于密集集成的单电子晶体管制造工艺。该制作过程的主要要点如下：首先，将电场形成的反演层用于量子点；其次，采用单或双原子层台阶（111）表面包围的凹槽结构减小反转层面积。最后，采用Si…More（100）衬底各向异性刻蚀和超高真空退火的方法制备凹槽结构。采用二维电容分析方法对该单电子晶体管的器件性能进行了仿真，并对器件的最佳尺寸进行了估计。制作了该尺度的单电子晶体管，并对其电学性能进行了表征。此外，为了进一步缩小器件的尺寸，对电子束光刻工艺进行了研究，并实现了0.05 μ m线图的制作。(3)非对称隧道势垒单电子器件的设计与制作提出了非对称隧道势垒单电子器件，并对其性能进行了仿真。结果表明，隧穿电流的方向性和电容与电阻之间的相关性较小，使得制作高性能的单电子器件变得容易。进一步阐明了非对称隧道势垒不仅在实现布尔逻辑方面具有优势，而且在实现二进制决策图（BDD）等非布尔逻辑方面也具有优势。少

(1) Formation of step-terrace structures using Si surface with small misorientationsFormatio of Single or Double atomiclayr steps was achieved with high cotrollability by annealing of Si (100) substrates with small misorientations under ultra-high vacuum condition. Samples were heated by passing current through them and the misorientation angles of Si (100) substrates are 4ﾟ and 1ﾟ toward (110) direction.(2) Design and fablication of single electron transistor using a small island surrounded by group of surfaces with same orientationThe fablication process of single electron transistor favarable for dense integration was proposed. Principle points of this fablication process were as followed. Firstly, the inversion layr formed by electric field was used for quantum dot. Secondly, the area of inversion layr was reduced using recess structure surrounded by (111) surfaces with single or double atomiclayr steps. Finally, the recess structure was fablicated by both anisotropic etching of Si … More (100) substarte and annealing the substrate under ultara-high vacuum condition.Device performance of this single electron transistor was simulated by 2-dimentional capacitance analysis and the optimum device scale was estimated. Single electron transistor with this scale was fablicated and its electrical properties also characterized.In addition, electron beam lithography process was examined for further scale down of this device and fablication of 0.05mum line pattern was achieved.(3) Design and fablication of single electron device with asymmetric tunnel barrierSingle electron device with asymmetric tunnel barrier was proposed and its performance was simulated. It was demonstrated that directionality of tunneling current and less correlation between capacitance and resistanece makes it easy to fablicate single electron device with high performance.Furthermore, it was made clear that asymmetric tunnel barrier have advantages for realizing of not only boolean logic but also non boolean logic like binary decission diagram (BDD). Less