A Study on Wide Bandwidth and Low Power Inductive-Coupling Inter-Chip Wireless Communication

由于在大规模集成电路的制造过程中通过缩放来提高晶体管的速度和集成度，计算速度呈指数级提高。另一方面，传统的大规模集成电路系统通过印制板实现，由于芯片间的距离和10个通道数量的限制，使得传输速率受到限制。这使得芯片间的传输速率和计算速度之间的性能差距越来越大。目前，芯片间通信已成为决定整个LSI系统性能的关键因素。三维堆叠技术作为一种有望解决这一问题的技术，在大规模集成电路系统中已成为研究的热点。本研究提出的层叠式芯片间感应通信是一种利用芯片内电感之间的感应耦合作为输入输出通道的芯片间无线通信技术。该技术的建立成为实现高性能LSI系统的关键。在此基础上，建立了最小化感应耦合通道面积的设计理论，并提出了减小通道间串扰的技术。利用该技术，实现了高密度通道测试芯片的设计、制造和评估，实现了芯片间的高速通信。采用所提出的电路技术设计了阵列信道。制作了测试芯片并对其性能进行了评价。四相时分多址（TDMA）是通过相位插补电路产生四相时钟来实现的。利用时分多址减少串扰，使信道阵列间距减小到30 μ m，使阵列面积达到1mm^2。通过布置1024个电感耦合通道，提高了通信性能（BER <10^<-13>）和带宽（1Tb/s）。通过将调制方案改为双相调制方案，提高接收机的噪声容限，可使发射功率降低2mW。少

The computation speed shows an exponential improvement due to the improvement over speed and integration of transistor by scaling on LSI fabrication process. On the other hand, conventional LSI system by printing board implementation, the transmission rate of inter-chip is limited because of the distance and restriction of the number of 10 channels. As a result the performance gap between transmission rate of inter-chip and computation speed became expanded. Nowadays, inter-chip communication becomes main key factor which determines performance of overall LSI system. 3-D stacked implementation in LSI system is a hot topic as a technique which is expected to solve the issue. Stacked inter-chip inductive communication which is proposed in the study is a inter-chip wireless communication technology where inductive coupling between inductors mounted in chip is used as input-output channels. Establishment of the technology becomes the key to realize high performance LSI system. In the study … More , Design theory for minimizing area of inductive coupling channels is established and the technique to reduce crosstalk between the channels, an issue occurs when channels are arranged, is proposed. By utilizing the technology, design, fabrication and evaluation of test chip with channels arranged in high-density are held and realization for high-speed inter-chip communication became the purpose of the study. Array channels with mounted proposed circuit technology are designed. Test chip is fabricated and the performance is evaluated. 4-phase Time Division Multiple Access (TDMA) is realized by creating 4-phase clock from phase-interpolation circuits. Crosstalk can be reduced by occupying Time Division Multiple Access and channel array pitch can be reduced to 30 μ m. As a result, 1mm^2 area of array is achieved. By arranging 1024 inductive coupling channel, communication performance (BER <10^<-13>) and wide bandwidth (1Tb/s) are improved. By changing modulation scheme into Bi-phase modulation scheme and improving receiver's noise-tolerance, 2mW of reduction in transmission power is achieved. Less