Fundamental study on design for testing of multi-layer structure VLSIs

电子束测试系统已被广泛应用于大规模集成电路内部信号行为的测试，但随着大规模集成电路制造技术的进步，设计多层结构的大规模集成电路已成为一种趋势。这种多层结构导致EB测试系统的可测试性降低，为了缓解测试LSI的困难，我们开发了测试垫引入工具，并提出了电流测试点来补充电压测试点，前一测试垫是指最上层的电极连接到下层的待测电极。我们设计了面积尽可能小的测试板单元，以便用EB测试仪进行探测。然后确定测试焊盘的数量和插入位置，以将故障区域大小缩小到指定数量的原始单元。通过将测试板引入工具应用于自制的8位微处理器LSI，考察了EB测试系统可测试性的提高和延迟时间等性能的劣化。结果表明，通过引入50个测试焊盘，故障区面积由约1300个改善到100个，性能恶化可以忽略不计，当控制信号设置为测试模式时，后一个电流测试点通过具有规定值的电流。通过检查电源总电流是否等于规定电流值的总和，我们就可以知道被测设备(DUT)是否有故障。当控制信号被设置为正常模式时，DUT执行正常操作。建立了工艺变化等多种约束条件下电流测试点单元的设计方法。

The electron beam (EB) test system has been widely used to measure internal signal behavior in LSI.However, with an advance in the LSI manufacturing, there has been a tendency to design an LSI with a multi-layer structure. This multi-layer structure causes the decrease in testability of the EB test system.In order to alleviate the difficulties in testing LSIs, we develop the test pad introduction tool and propose the current test points that complement the voltage test points.The former test pad means the electrode on the uppermost layer connected to the electrode on the lower layer to be measured. We designed the test pad cell with area as small as possible to be probed with an EB tester. Then the number and the insertion positions of test pads are determined to narrow down the faulty area size to the specified number of primitive cells. By applying the test pad introduction tool to the self-made 8-bit microprocessor LSI, the improvement in testability of the EB test system and the performance deterioration such as the delay time were examined. Results shows that the faulty area size of about 1300 was improved to 100 by introducing 50 test pads and the performance deterioration could be neglected.The latter current test point passes an electric current with a prescribed value when the control signal is set at a test mode. By checking whether the total power supply current is equal to the sum of the prescribed current values or not, we know the device under test (DUT) is faulty or not. When the control signal is set at a normal mode, the DUT performs normal operations. We established the design method of current test point cells under various constraints such as process variations.