Studies on logic design and testing methodology for very high performance VLSIs

深亚微米和高性能电路通常存在由噪声、工艺和功耗引起的延迟变化问题。大多数电路的制造缺陷也会导致与时序相关的故障。为了保证高性能电路的高可靠性，我们研究了时序故障的设计和测试问题。路径时延故障模型是著名的待测定时故障模型之一。在路径延迟故障的测试生成中，在测试生成之前识别不可测路径是很重要的。我们首先开发了一种方法来识别给定电路的不可测路径。虽然以前提出的方法需要很长的时间来处理大量的路径，我们的方法可以处理这样的电路与短的计算时间，而不牺牲不可测路径识别的能力。此外，我们提出了一种方法来提取一组应该测试，更可能是错误的路径。接下来，我们考虑了同步时序电路中触发器数据保持时间要求的验证问题，这与触发器建立时间误差（如路径延迟故障）不同。三个故障模型和测试生成过程中提出的是有关的电路中存在的短路径。最后，我们研究了一种使用低速LSI测试仪检测高性能电路时序故障的设计和测试方法。在使用低速测试仪的情况下，测试压缩是必要的技术。为了得到一个可高度压缩的测试集，我们提出了一种识别给定测试集的无关输入的方法。我们还提出了一种方法来压缩测试集与无关输入，并表明所提出的方法的有效性。

Deep sub-micron and high-performance circuits often have a delay variation problem caused by noise, process, and power. Most of manufacturing defects of the circuits cause timing-related failures too. In order to guarantee high reliability of the high performance circuits, we investigated design and test issues on timing failures. Path delay fault model is known as one of a well-known timing failure to be tested. In test generation for path delay faults, it is important to identify untestable paths prior to test generation. We first developed a method to identify untestable paths of a given circuit. Though methods proposed earlier required long time to process a circuit with large number of paths, our method could deal with such a circuit with a short computation time without sacrificing the ability of untestable path identification. In addition, we proposed a method to extract a set of paths which should be tested and more likely be faulty. Next we considered the problem of validating flip-flop data hold time requirements in synchronous sequential circuits, which is different from flip-flop set-up time errors like path delay faults. Three fault models and a test generation procedure were proposed that are related to the presence of short paths in the circuit. Finally we investigated a methodology of design and test for detecting timing faults of high performance circuits using a low-speed LSI tester. In case of using a low-speed tester, test compression is a necessary technique. In order to obtain a test set which can be highly compressed, we developed a method for identifying don't care inputs of a given test set. We also proposed a method to compress a test set with don't care inputs and showed the effectiveness of the proposed method.