Development of a Real-Time Reconfigurable Signal Processor for Image Recognition

最近，我们提出了一种基于纯相位相关(POC)的面向DSP的图像识别算法。为了将该算法应用到实际的图像识别任务中，实/复混合数据的高速计算是必不可少的。在本研究项目中，我们研究了一种用于基于POC的图像识别的信号处理器架构。非二进制数据表示，如冗余复数系统和高基冗余数系统，用于执行快速的实数/复数混合计算。1.提出了一种实数/复数可重构运算器，该运算器可以在三种不同的工作模式下改变其结构，并在0.5um的CMOS片上实现。这三种模式实现了复数乘法、双倍长实数乘法和实数乘加运算。重新配置开销显著较低，对应的…仅增加8.9%更多的晶体管数量。提出了一种冗余复数乘法器的设计方案，并用0.5um芯片进行了工艺实现。与使用标准逻辑综合工具设计的复数乘法器相比，芯片面积、互连延迟和功耗分别降低了33.7%、16.9%和18.4%。提出了一种基于符号加权(Sign-Weight)算法的可配置乘法器，并在0.35um芯片上实现了该加法器。该芯片可以实现10 MHz-100 MHz范围内高采样率的FIR滤波。提出并制作了一种用于三维图像处理的并行除法器和CORDIC矢量旋转器。高基冗余数系统的使用使得迭代算术运算的低延迟实现成为可能。除了上述结果外，还研究了基于POC的图像识别的各种应用。我们开发了一个使用分层纯相位匹配的3D(立体)视觉系统，并阐明了实现用于3D测量和对象识别的新信号处理器的体系结构要求。较少

Recently, we have proposed a DSP-oriented image recognition algorithm based on Phase-Only Correlation (POC). For applying the proposed algorithm to practical image recognition tasks, high-speed computation of real/complex-mixed data is essential. In this research project, we investigated a signal processor architecture for POC-based image recognition. Non-binary data representations, such as redundant complex number systems and high-radix redundant number systems, are employed to perform fast real/complex-mixed computation. We have developed the key components for the signal processor as listed below:1. A real/complex reconfigurable arithmetic unit, that can change its structure for three different operation modes, has been proposed and fabricated in 0.5um CMOS. The three modes realize complex-number multiplication, double-length real-number multiplication, and real-number multiply-add operation. The reconfiguration overhead is significantly low, which corresponds to only 8.9% increase … More of transistor count.2. A redundant complex multiplier has been proposed and fabricated in 0.5um CMOS. The chip area, interconnect delay and power consumption are reduced to 33.7%, 16.9% and 18.4%, respectively, compared with a complex-number multiplier designed by a standard logic synthesis tool.3. A configurable multiply-adder based on SW (Signed-Weight) arithmetic has been proposed and fabricated in 0.35um CMOS. The fabricated chip can perform FIR filtering with high sampling-rate around 10MHz-100MHz.4. A parallel divider and a CORDIC vector rotator for 3D image processing have been proposed and fabricated. The use of high-radix redundant number systems makes possible low-latency implementations of iterative arithmetic operations.In addition to the above results, various applications of POC-based image recognition have been investigated. We developed a 3D (stereo) vision system using hierarchical phase-only matching, and clarified architectural requirements toward the implementation of a new signal processor for 3D measurement and object recognition. Less