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A New Functional MOS Transistor Featuring Neuron Functions

A New Functional MOS Transistor Featuring Neuron Functions
一种具有神经元功能的新型功能 MOS 晶体管
批准号:
02402032
负责人:
SHIBATA Tadashi
金额:
$8.64万
依托单位国家:
日本
项目类别:
Grant-in-Aid for General Scientific Research (A)
财政年份:
1990
资助国家:
日本
项目状态:
已结题
起止时间:
1990 至 1991

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中文摘要
翻译
一种新的功能MOS晶体管已经被开发出来,它的工作比单纯的开关器件更智能。功能晶体管在门级计算所有输入信号的加权和,并基于这种加权和运算的结果控制晶体管的“开”和“关”。由于这种器件的功能与生物神经元非常相似,因此将其命名为神经元MOSFET或Neumos(简称nuMOS)。该器件由浮动栅和多个与浮动栅电容相互作用的输入门组成。由于门级求和运算是在利用电容耦合效应的电压模式下执行的,因此在计算过程中基本上不会产生功耗,这使得该器件成为ULSI实现的理想选择。基于一个简单的晶体管模型和实验,分析了神经元MOSFET的基本特性以及简单电路模块的基本特性。利用其非常强大的功能,设计了一些有趣的…电路已经探索了更多的应用。描述了Neumos反相器和神经元电路、可变阈值晶体管和反相器、线性电阻、Neumos源极跟随器电路和单门D/A转换器。还提出了由Neumos晶体管实现的软硬件逻辑电路的概念。该电路表现出一个非常有趣的特征,即电路的逻辑功能可以由外部信号任意改变,而不需要对硬件配置进行任何改变。当固定功能逻辑电路由nuMOS晶体管实现时,与传统的CMOS设计对应电路相比,晶体管的数量以及互连的数量可以显著减少。例如,4位闪存A/D转换器可以只由28个晶体管构成,尽管传统设计需要398个晶体管。采用双层多晶硅工艺制作测试电路,通过实验验证了这些电路的基本工作原理。较少
英文摘要
A new functional MOS transistor has been developed which works more intelligently than a mere switching device. The functional transistor calculates weighted sum of all input signals at the gate level, and controls the "on" and "off" of the transistor based on the result of such a weighted sum operation. Since the function is quite analogous to that of biological neurons, the device is named a neuron MOSFET or neuMOS (nuMOS) in short. The device is composed of a floating gate and plural of input gates that are capacitively interacting with the floating gate. As the gate-level sum operation is perfomied in a voltage mode utilizing the capacitive coupling effect, essentially no power dissipation occurs in the calculation, making the device ideal for ULSI implementation. The basic characteristics of neuron MOSFET's as well as of simple circuit blocks are analyzed based on a simple transistor model and experiments. Making use of its very powerful function, a number of interesting circuit a … More pplications have been explored. neuMOS inverters and neuron circuits, variable threshold transistors and inverters, linear resistors, and neuMOS source follower circuits and single gate D/A converters are described. The concept of a Soft Hardware Logic Circuit implemented by neuMOS transistors has been also developed. The circuit exhibits a very interesting feature that the logical function of the circuit is arbitrarily altered by external signals without any changes in the hardware configuration. When fixed function logic circuits are implemented by nuMOS transistors, the number of transistors as well as of interconnections can be dramatically reduced as compared to their conventional CMOS-design counterparts. 4-bit flash A/D converter, for instance, can be constructed by only 28 transistors although 398 transistors are required in conventional design. Basic operations of these circuits have been experinientally verified by fabricating test circuits using double polysilicon CMOS process. Less
期刊论文(17)
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会议论文
T,Shibata: "An Intelligent MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations" Technical Digest,International Electron Devicas Meeting 1991,Washington D.C.919-922 (1991)
T,Shibata:“具有门级加权和和阈值操作的智能 MOS 晶体管”技术文摘,1991 年国际电子设备会议,华盛顿特区 919-922 (1991)
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通讯作者:
T. Shibata and T. Ohmi: "A new-concept transistor realizing neuron functions by a single device" Nikkei Microdevices. 79. (1992)
T. Shibata 和 T. Ohmi:“通过单个器件实现神经元功能的新概念晶体管”Nikkei Microdevices。
DOI: --
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通讯作者:
T. Shibata and T. Ohmi: "An intelligent MOS transistor featuring gate-level weighted-sum and threshold operations" Technical Digest, International Electron Devices Meeting 1991, Washington D. C.919-922 (1991)
T. Shibata 和 T. Ohmi:“具有门级加权和和阈值操作的智能 MOS 晶体管”技术文摘,1991 年国际电子器件会议,华盛顿特区 C.919-922 (1991)
DOI: --
发表时间:
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作者: []
通讯作者:
T.Shibata: "An Intelligent MOS Transistor Featuring GateーLevel Weighted Sum and Threshold Operations" Technical Digest,International Electron Devices Meeting 1991,Washington D.C. 919-922 (1991)
T. Shibata:“具有门级加权和和阈值操作的智能 MOS 晶体管”技术文摘,1991 年国际电子器件会议,华盛顿特区 919-922 (1991)
DOI: --
发表时间:
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影响因子: --
作者: []
通讯作者:
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