Design for Fault-Tolerant Programmable Chips

研究结果如下：(1)、(2)、(3)、(4)。(1)容错设计我们提出了一种基于异构内核的SOC容错设计方案。通过数值计算结果验证了设计的有效性。我们还提出了一种缺陷和容错的SOC设计，该SOC由分层方式构建的核心组成，其中底层电路具有同质结构。我们将我们的策略应用于32位并行乘法器，以显示我们设计的效率。(2)FPGA测试提出了一种多上下文FPGA的测试方法。这种方法的优点是配置内存的写入次数很少。在此背景下，对FPGA测试、缺陷和容错设计的传统工作进行了综述。(3)VISI测试我们研究了以下测试研究方向：延迟故障检测的BIST设计和延迟故障检测的分析，两种使用SOC可编程内核测试测试电路的测试方法，以及分层结构的SOC BIST设计。(4)容错与恢复的体系结构我们提出了一种易于从互连网络死锁中恢复的方法，并通过对网络的分析来评估其性能。在这方面的研究中，我们提出了互连网络中的容错路由和基于容错虫洞的交换，使其能够回溯。

We have got the following results concerning (1),(2),(3),and (4).(1)Defect Tolerant DesignWe proposed a defect and fault tolerant design for SOC, which is built by cores having the heterogenieous structutures. We proved the efficiency of our design by numerical evaluation results. We also proposed a defect and fault tolerant design for SOC consisting of cores which arc built in hierachical manner and where the lowest level circuits have homogenious structures. We applied our strategy to 32-bits parallel multiplier to show the efficiency of our design.(2)FPGA TestingA test method for mufti-context FPGA has been proposed. This method has the advantage of having small number of writing times for configuration memory. In this context, survey for conventional works about FPGA testing, defect and fault tolerant designs have been made.(3)VISI TestingWe have investigated the following directions of research in testing: a design for BISTs for delay fault detection and analysis of delay fault detection, two test methods using programmable cores in SOC for testing circuits under the test, and design of BIST for SOC which are made in hierarchical structure.(4)Architecture for Fault Tolerance and RecoveringWe proposed an easily recovering method from deadlock in an interconnection network We evaluated the performance by the analysis of the network In this area of research fault tolerant routing in an interconnection network and fault tolerant wormhole-based switching making possible backtracking have been proposed.