Studies on High-Level Synthesis for Testability Based on Combinational Test Generation Complexity

本文提出了一类部分直通可测时序电路，它是非循环时序电路的一个子类，并适当地包含了一类全直通可测时序电路。本文还提出了部分可通时序电路测试集的有效生成方法和部分可通时序电路的设计算法。与传统的全扫描设计相比，在保持完全故障效率的情况下，本工作的结果有助于减少硬件开销以实现可测性。

This work proposed a class of partial thru testable sequential circuits.The class is a sub-class of acyclically sequential ones, and properly includes a class of full thru testable sequential ones. This work also proposed an efficient method for generating test sets for partial thru sequential circuits, and an algorithm for designing partial thrutestable sequential circuits. The result of this work contributes to the reduction in hardware overhead for testability compared with the conventional full scan design with keeping complete fault efficiency.