New approach to size selection and thin film growth of silicon quantum dots and applications

硅纳米晶体的完整升华是一个非常新颖和意想不到的观察。我已经使用这种方法将硅纳米晶体沉积在各种基片上，这些基片放置在生成的蒸汽中（蓝宝石板，石墨片，硅片和氮化金薄膜）。在高真空中蒸发和沉积纳米晶体的能力可能对尺寸控制制备新的纳米级量子限制结构有用。纳米颗粒的许多潜在用途都要求颗粒具有明确的尺寸。但在如此小的范围内实现这一目标并不容易，而且在此之前，这主要是一个试验和错误的问题。这种新型的硅纳米晶体完整升华为尺寸选择和薄膜制备提供了一种新的方法。应用的一个例子是用纳米晶体层取代浮栅存储器中传统的氧化层。目前，非易失性存储设备利用浮栅场效应晶体管技术来存储信息，这些设备有许多应用，例如移动电话，数码相机，摄像机，MP3播放器，数字游戏，ipod，闪存卡和可移动存储设备，这是一个快速增长的市场（2007年为400亿美元，比2006年增长12.9%）。在这种存储器器件中，电荷存储在硅浮栅上，该浮栅通过电介质隧道势垒与衬底分离。典型地，隧道势垒由一层薄薄的热生长SiO2层组成。这个隧道屏障控制了设备的保留时间和程序/擦除速度。当“程序”偏压施加到器件上时，电荷穿过势垒并在程序电压被移除后仍然存储在浮栅上。首先，由于隧道势垒必须能够在编程过程中注入电流并保持电荷，因此在设计集成隧道势垒的存储器件时必须做出妥协。当势垒相对较厚时，可以实现较长的电荷保持时间，但需要更高的电压（和更长的时间）来编程和擦除浮栅。当势垒较薄时，编程和擦除过程将更加迅速，但电荷泄漏的增加将减少保留时间。如果由硅纳米晶体（又名量子点）组成的单层取代SiO2层，将会有效地降低势垒。这种势垒降低效应将允许隧道电流密度的增加和随后的浮栅程序/擦除速度的增加。其次，对于一个正常的闪存来说，一个主要的问题是氧化物的不均匀性造成的；如果存在漏电流密度较大的薄弱点，它就充当了一个水槽，所有存储在浮栅中的电荷都将通过它泄漏出去。这个问题随着氧化层的变薄而增加。同样，如果用纳米粒子代替浮栅，薄弱点只会影响少量纳米粒子，而对储存在其他粒子中的电荷没有影响。因此，在本设计中，隧道势垒氧化物和层间氧化物的厚度都可以在不牺牲记忆保留时间的情况下减小。第三，由于设备阈值的变化取决于粒度，因此宽的粒度分布将冲掉操作阈值。因此，大小选择是这个应用程序的一个大问题。这个研究项目是欧洲第一个这样的研究项目，是英国进入纳米晶体存储设备这一主要领域的一个机会。在这里的研究计划中，我们将研究纳米晶体在真空中蒸发-沉积过程的动力学，这将有助于发展纳米晶体尺寸选择的新方法。这种新方法将进一步用于形成尺寸可控的纳米晶体薄膜，可用于取代浮栅存储器件中的SiO2层。

The intact sublimation of silicon nanocrystals is an extremely novel and unexpected observation. I have used this method to deposit silicon nanocrystals on a variety of substrates placed in the resulted vapour (sapphire plates, graphite sheet, silicon wafer and gold nitride films). The ability to evaporate and deposit nanocrystals in high vacuum may be useful for the size-controlled preparation of new nanoscale quantum-confined structures. Many of the potential uses of nanoparticles demand that the particles have well defined sizes. But this is not easy to achieve at such small scales, and it has previously been largely a matter of trial and error. This novel intact sublimation of silicon nanocrystals could provide a novel method for size selection and thin film preparation. One example of applications is replacing the conventional oxide layer in floating gate memory devices with a layer of nanocrystals. Currently, nonvolatile memory devices utilize floating gate field-effect transistor technology to store information, and these have many applications e.g. mobile phones, digital cameras, camcorders, MP3 players, digital games, iPods, flash cards and removable storage devices, which is in a rapidly growing market ($40 billion in 2007, up 12.9% from 2006). In such memory devices, charge is stored on a silicon floating gate that is separated from the substrate by a dielectric tunneling barrier. Typically, the tunneling barrier consists of a thin thermally-grown SiO2 layer. This tunneling barrier controls the retention time and the program/erase speed of the device. When a ''program'' bias is applied to the device, charge tunnels through the barrier and remains stored on the floating gate after the program voltage is removed. Firstly, since the tunneling barrier must be able to inject a current during programming and to retain charge, a compromise must be made when designing memory devices that integrate a tunneling barrier. When the barrier is made relatively thick, long charge retention times are achieved, but a higher voltage (and a longer time) is required to program and erase the floating gate. When the barrier is thin, the programming and erase process will be more rapid, but increased charge leakage will reduce the retention time. If a monolayer comprised of silicon nanocrystals (aka quantum dots) was to replace the SiO2 layer, an effective lowering of the barrier would be observed. This barrier lowering effect will allow an increase in the tunnel current density and a subsequent increase in the floating gate program/erase speed. Secondly, for a normal flash memory, a major problem is caused by the non-uniformity of the oxide; if there is a weak spot where the leakage current density is larger, it acts as a sink and all stored charges in the floating gate would leak away through it. This problem increases with the thinning of the oxide layer. Again, if the floating gate is replaced with nanoparticles the weak spot will only affect a small number of nanoparticles and has no effect on the charge stored in other particles. Therefore, in this design, the thickness of both tunneling barrier oxide and inter-level oxide can be reduced without sacrificing the memory retention time. Thirdly, since the shift in the device's threshold depends on the particle size, a wide size distribution would wash out the operating threshold. Thus the size selection is a big issue for this application. This research project is the first such research in Europe and is an opportunity for UK to enter this major area of nanocrystals based memory devices.In the research program described here we will study the dynamics of the evaporation-deposition process of nanocrystals in vacuum, which will contribute to the development of the novel method for nanocrystals selection by size. This novel method will be developed further for forming size-controlled nanocrystal thin films, which could be used to replace the SiO2 layer in floating gate memory devices.