Zero-change manufacturing of photonic interconnects for silicon electronics

硅电子行业在开发新产品方面面临两大挑战：对单个芯片上处理能力水平不断提高的需求，以及运行这些芯片所需的能量。这两个挑战是相互关联的，因为集成到芯片中的组件和通信链路越多，相关的能耗就越高。虽然单个芯片的能耗相对较低，但考虑到每年生产的单位数量庞大，达到数十亿的数量级，这将迅速扩展到环境水平。目前，大型数据中心消耗的电力约占全球电力需求的1%，因此集成芯片能耗的任何效率提高都将产生重大影响。随着器件尺寸达到基本的物理极限，芯片设计人员正在开发新的架构，以继续提供芯片性能的增长。这些设计需要跨越毫米长度尺度的高带宽通信，目前实现为简单的电子轨道。通过用光学互连代替这些轨道，可以降低系统功耗并提高通信带宽。任何替代技术面临的根本挑战是，它必须与当前的电子制造业兼容，在过去几十年中，电子制造业已经进行了大量投资。该项目将开发一种光学互连层，其链路功耗低于等效的电子线路。光学层将被实现为可以插入硅器件及其封装之间的薄膜芯片，这意味着该过程相对于电子芯片的制造是零变化的。斯特拉斯克莱德大学和谢菲尔德大学在光电膜系统的超高精度微组装方面的最新进展将使设计成与大规模生产兼容的两阶段工艺成为可能。首先，薄膜光源，波导和探测器将组装在一个玻璃芯片，包括电气通孔。这种具有集成光学互连的插入器将使用微组装工艺集成在电子芯片及其封装之间。该项目得到了工业合作伙伴Alter Technologies和Fraunhofer UK的支持，他们将提供光电封装和光学系统工程方面的资源和专业知识。这将确保新的工艺开发符合工业标准和设计规则。该提案符合EPSRC的ICT和未来制造主题以及未来系统光子学优先事项，涉及特定的投资组合领域，如制造技术，光通信，光器件和子系统，光电器件和电路，组件和系统。到项目结束时，我们将展示一种光传输链路，其能耗低于同等的电子线路。该链路将与商业上可用的硅收发器芯片集成，以证明将该技术开发为硅电子行业的后端工艺的可行性。

The silicon electronics industry has two major challenges in the development of new products: demand for increasing levels of processing power on a single chip and the amount of energy required to run these chips. The two challenges are linked, since the more components and communications links that are integrated into the chip, the higher the associated energy usage. While the energy consumption of a single chip is relatively low, this rapidly scales to environmental levels when considering the huge volume of units produced each year is in the order of 10's of billions. Already, large scale data-centres consume around 1% of global electricity demand, so any efficiency gains in the energy consumption of integrated chips will have significant effects. As device dimensions reach fundamental physical limits, chip designers are developing new architectures in order to continue to deliver growth in chip performance. These designs require high bandwidth communications across millimetre length scales, currently realised as simple electronic tracks. By replacing these tracks with optical interconnects, system power consumption can be reduced and communications bandwidth improved. The fundamental challenge for any alternative technology is that it must be compatible with current electronics manufacturing, where vast investments have been made over the last decades. This project will develop an optical interconnect layer that has a link power consumption lower than equivalent electronic lines. The optical layer will be realised as a thin film chip that can be interposed between the silicon device and its packaging, meaning that this process is zero-change with respect to the manufacture of the electronic chips. Recent advances pioneered at the Universities of Strathclyde and Sheffield in ultra-high precision micro-assembly of opto-electronic membrane systems will enable a two stage process that is designed to be compatible with production at scale. Firstly, membrane optical sources, waveguides and detectors will be assembled on a glass chip that incorporates electrical vias. This interposer with integrated optical interconnects will be integrated between the electronic chip and its packaging using micro-assembly processes. The project is supported by industrial partners Alter Technologies and Fraunhofer UK who will provide resources and expertise in opto-electronic packaging and optical systems engineering. This will ensure new process developments with industrial standards and design rules.The proposal aligns with EPSRC's ICT and Manufacturing the Future themes and the Photonics for Future Systems priority, addressing specific portfolio areas such as Manufacturing Technologies, Optical Communications, Optical Devices & Subsystems, Optoelectronic Devices & Circuits, Components & Systems. By the end of the project we will have demonstrated an optical transmission link with energy consumption lower than an equivalent electronic line. This link will be integrated with a commercially available silicon transceiver chip to demonstrate feasibility of developing this technology as a back-end process in the silicon electronics industry.