Silicon Carbide MOSFETs

项目计划细节包括关键里程碑- UMOS技术包括一个垂直通道区域，毗邻通常的横向平面。这种旋转会对界面原子的排列产生影响，因为4H-SiC的结构会偏离取向。由于这种不同的方向所提供的方面，在这种装置中应该实现稍高的移动性。第一个里程碑将是制造界面陷阱密度值等于或低于SiC氧化层的UMOS技术。通过对界面阱密度、迁移率和迟滞特性的分析，设计并制备了UMOS电容器。在这一里程碑成功后，第二个里程碑将是制造单个UMOS功率晶体管电池：将设计和制造一个UMOSFET。将为此设计掩模，并在单个晶圆上设计DMOS晶体管。两种技术的特点可以直接比较。将对UMOS装置进行表征。然而，如果在第一阶段，UMOS技术在其当前的承载能力方面显示出很少的希望，其他团队成员将致力于DMOSFET的设计，我可以加入他们，完成该器件的表征任务。第三个里程碑将是进行可靠性分析：评估两个功率MOSFET器件的可靠性，通过检查器件在某些参数（如温度和电流）下运行一段时间时的故障概率来解决潜在的可靠性问题。项目概述：碳化硅是一种宽带隙半导体，具有特殊的电气和其他材料特性，适用于电力电子应用。但其载流能力和I-V迟滞性很差。我们最近已经证明，栅极堆栈的纳米尺度工程可以实现主要的（10倍）性能改进（DOI: 10.1109/TED.2019.2901310）。该博士项目将以这种新方法为基础，研究功率mosfet的I-V性能和可靠性。研究将包括设备制造、表征和分析。

Details of project plan including key milestones - UMOS technology consists of a vertical channel region, adjacent to the usual lateral plane. This rotation will have an impact on the arrangement of atoms at the interface since the structure of 4H-SiC will be off-orientated. A slightly higher mobility should be achieved in this device due to aspects provided by this different orientation.The first milestone will be fabricating UMOS technology with interface trap density values of a magnitude equal to or lower than that seen in SiC oxide layers.A UMOS capacitor will be designed and fabricated with analysis of interface trap density, mobility and hysteresis.Upon success of this milestone, the second milestone will be fabrication of a single UMOS power transistor cell:A UMOSFET will be designed and fabricated. A mask will be designed for this and a DMOS transistor to be on a single wafer. The two technologies characteristics can be directly compared. The UMOS device will be characterised. However, if in the first phase, the UMOS technology shows little promise in its current carrying capability, other team members will be working on design of the DMOSFET and I can join them with the task of characterisation of this device.The third milestone will be carrying out reliability analysis:Assessing the reliability of both power MOSFET devices, addressing potential reliability problems by examining failure probability when the device is operated under certain parameters (such as temperature and current) for a period of time. Summary of the proposed project - Silicon Carbide is a wide band-gap semiconductor with exceptional electrical and other material properties for power electronics applications. But it has very poor MOS current carrying capability and I-V hysteresis. We have shown recently that major (10x) performance improvements can be achieved by nm scale engineering of the gate stack (DOI: 10.1109/TED.2019.2901310). This PhD project will build on this new approach and look at both power MOSFETs I-V performance and reliability. The research will include device fabrication, characterisation and analysis.