Self-Timed Event Processor

本研究的领域是异步和反应式事件处理和处理硬件的设计，综合和验证。该硬件预计将在并发，分布式和实时计算网络的环境中工作。这些网络既包括真正的分布式系统，如无线网络、传感器网络和实时网络，也包括具有分布式处理的高度集成的片上网络计算机。这些系统正变得越来越复杂，并且处理元件之间的通信量正在增加。因此，处理构成业务的事件可以决定系统性能和特性的大部分。在未来的计算网络中，不确定性和非确定性都是不可避免的，这首先是因为不同的功能元件的不同时序要求。其次，随着半导体技术的进步和集成度的增加，并发和分布式系统实现导致更大的复杂性和非确定性（国际半导体技术路线图（ITRS-05）设计文档强调多个时钟域和源同步信令，并预测自定时块的网络）。现有的设计硬件事件处理系统的方法是相当特设的，没有系统的建模和综合support.From这一点来看，这里提出的项目可能会产生重大影响的工业界以及学术界。我们的目标是开发一种设计和合成方法的自定时硬件子系统（称为自定时事件处理器或步骤）。STEP将处理来自多个源的异步和非确定性事件，并根据用户规范进行响应（例如通过分配资源，其可用性也可能异步和非确定性变化）。自定时是指从表示事件本身的信号中导出触发信息，并且STEP可以用于与诸如处理器或通信设备之类的现成服务IP核形成虚拟自定时反应服务块。我们建议，这种方法将包括一个通用的STEP体系结构，技术推导出线延迟意识的设计架构的组成部分，并验证这种设计的技术。一般的数学建模技术的步骤在各个层次的细节的基础上Petri网将形成的基础上的设计/合成和验证工作。我们的目标是开发设计和合成技术的程度，该过程变得系统化，高度算法化，并可能自动化，并将涵盖所有层次的细节下降到硬件门级原理图。我们认为，STEP技术将是事件处理领域的一个进步，并将有助于ITRS-05中设想的自定时块系统的实现。该项目的合作者将包括MBDA英国有限公司，该公司是欧洲领先的导弹控制实时分布式系统设计技术提供商。该公司率先推出了Butler（获得2004年Queed企业奖）和Route-Table技术，为STEP提供了激励性的起始想法，例如平铺电路架构。

The field of this research is the design, synthesis and verification of asynchronous and reactive event handling and processing hardware. This hardware is expected to work in an environment of concurrent, distributed, and real-time computation networks. These networks include both truly distributed systems such as wireless networking, sensor networks, and real-time networks as well as highly integrated on-chip networked computers with distributed processing. These systems are becoming more complex, and the traffic among the processing elements is increasing. Therefore handling the events which make up the traffic may determine much of the system performance and characteristics. Both asynchrony and non-determinism are inevitable for computation networks in the future, firstly because of the different timing requirements of different and diverse functional elements. Secondly, concurrent and distributed system implementations lead to greater asynchrony and non-determinism as semiconductor technology advances and the degree of integration increases (the International Technology Roadmap for Semiconductors (ITRS-05) Design document emphasizes multiple clock domains and source-synchronous signalling, and predicts networks of self-timed blocks). Existing methods of designing event-handling systems in hardware are rather ad hoc and have no systematic modelling and synthesis support.From this point of view, the project proposed here may have a major impact on the industrial as well as academic community. We aim to develop a design and synthesis method for self-timed hardware subsystems (called self-timed event processors or STEPs). STEPs will handle events arriving asynchronously and non-deterministically from multiple sources, and respond (such as by allocating resources, whose availability may also be asynchronously and non-deterministically changing) according to user specifications. Self-timing is in the sense that the triggering information is derived from the signals representing the events themselves, and STEPs may be used to form virtual self-timed reactive service blocks with off the shelf service IP cores such as processors or communications devices. We propose that this method will include a general STEP architecture, techniques for deriving wire delay aware designs for the integral parts of the architecture, and techniques for verifying such designs. A general mathematical modelling technique for STEPs at all levels of detail based on Petri nets will form the basis for the design/synthesis and verification work. We aim to develop the design and synthesis techniques to a degree where the process becomes systematic, highly algorithmic, and potentially automatic, and will cover all levels of detail down to hardware gate level schematics. It is our view that STEP technology will be a step forward in the event handling front, and will help towards the realization of systems of self-timed blocks envisioned in ITRS-05.The project will involve as a collaborator MBDA UK Ltd, a leading European privider of design technology for real-time distributed systems for missile control. The company has pioneered the Butler (awarded with The Queed's Award for Enterpise 2004) and Route-Table technologies, which provide stimulating starting ideas for STEP, such as tiled circuit architecture.