Synthesis and Optimisation of Designs Based on Novel Canonical Algebraic Structures

行为综合是电子系统级（ESL）设计的重要组成部分，它提供了优化设计的最有效手段，允许设计者专注于设计抽象的最高层次，即行为和算法层次。毫无疑问，行为综合对复杂集成电路（ic）和用CAD工具设计的片上系统（SoC）的质量影响最大。尽管在过去的二十年中，行为合成取得了许多进展，但现有的合成系统在将初始设计规范转换为硬件方面仍然无效。特别是，现有的工具依赖于单一的、固定的数据流图（DFG），从设计规范中提取，并映射到硬件上。本研究提出了一种基于计算的功能（而不是结构）表示的行为综合的系统方法。特别地，提出了一种新的方法来执行有效的因式分解多项式表达式从算法设计描述使用两个新的，规范的代数结构：1)泰勒展开图（TED）和2)伽罗瓦场决策图（GPDD）。作为规范表示，这些结构可以捕获整个结构解决方案类，而不是使用当前方法获得的单个DFG。通过本研究提出的一组新颖的功能分解过程，可以将初始功能表示转换为一组结构表示（数据流图，DFG），从中可以为特定的设计目标（如电路面积，延迟，功耗或性能）选择最优表示，从而实现高效的硬件实现。所提出的方法将为设计师提供一种工具来执行有效的架构解决方案探索，而不需要重写和重新合成原始规范来寻找最佳解决方案。

Behavioral synthesis, an important part of Electronic System Level (ESL)design, provides the most effective means to optimize the design by allowingthe designer to concentrate on the highest level of design abstraction, namely behavioral and algorithmic levels. Behavioral synthesis has unquestionably the greatest impact on the quality of complex Integrated Circuits (ICs) and systems on chip (SoC) designed with CAD tools. Despite many advances in behavioral synthesis over the past two decades, existing synthesis systems are still ineffective in translating the initial design specification into hardware.In particular, existing tools rely on a single, fixed data flow graph (DFG), extracted from the design specification, and mapped onto hardware.This research proposes a systematic approach to behavioral synthesis based on functional (rather than structural) representation of the computation. In particular, a new method is proposed to perform efficient factorization and decomposition for polynomial expressions derived from algorithmic design descriptions using two novel, canonical algebraic structures:1) Taylor Expansion Diagram (TED), and2) Galois Field Decision Diagrams (GPDD).As canonical representations, these structures can capture an entire class of structural solutions, rather than a single DFG obtainable with current methods. Through a set of novel functional decomposition procedures proposed in this research, the initial functional representation can be converted into a set of structural representations (data flow graphs, DFG), from which an optimum one can be chosen for a particular design objective, such as thecircuit area, latency, power, or performance, leading to efficient hardware implementations.The proposed method will equip the designers with a tool to perform efficient exploration of architectural solutions, without a need to rewrite and re-synthesize the original specification in search for the best solution.