Renaissance Germanium

锗，作为一种半导体材料，正经历着复兴——甚至可能与硅相媲美。随着硅的终结游戏升温，锗正吸引着巨大的兴趣。许多人大胆地认为，在硅发展的预期终点（2020年左右）之后，它将成为维持类硅技术和相关设备的潜在候选者，并将该技术带入令人兴奋的新领域和性能体系。这一建议着手探索一些有趣的方面和结果的基本电子结构的Ge以前没有研究过。有很好的理论论据表明，如果载流子沿非常规晶体学方向移动，并且锗处于应变状态，则某些关键性能参数可以显着提高。我们将研究这些新环境如何影响载流子（电子和空穴）的速度/迁移率和有效质量，以及阻碍它们运动（散射）的过程。该项目将由三个英国大学小组进行，他们在应变锗的外延生长（沃里克大学）、纳米级结构表征的透射电子显微镜（谢菲尔德大学）和载流子输运模型（格拉斯哥大学）方面具有独特的地位，并在国际上享有盛誉。华威大学的工业标准CVD生长系统使我们处于一个独特的位置，可以为这一研究领域做出贡献，并在项目早期提供高质量Ge结构的良好前景。IMEC的参与，欧洲领先的纳米加工实验室，将给我们无与伦比的访问工具，没有在英国提供。我们的知识产权将得到充分保护，可以被英国的许多公司利用。主要目标是研究这些未经试验的二维载流子迁移方向，并寻找与传统（100）方向相比载流子迁移率的显着增强。类似的研究目前正在硅中进行，现在是时候在Ge中进行探索了。鉴于IMEC最近在使用硅加工技术制造Ge器件方面取得的进展，这是特别及时的。该计划包括三个集成的工作包：WP1 -应变锗通道结构的生长和加工：外延工艺将被开发，结构表征包括高分辨率TEM，以及用于电测量的简单结构。WP2 -调制掺杂埋没沟道结构：初步评估和筛选取向和应变对空穴和电子传输的影响，快速瞄准优化结构，特别避免任何可能对电子传输有害的加工干扰效应。测量结果将由格拉斯哥设备建模小组用于开发/完善该材料系统的基本散射和迁移率模型，并为最终结构选择提供指导。WP3 -表面沟道器件结构：包含栅极的结构，用于调制载流子数量并使其成为有源器件。栅极与通道被一层非常薄的新型（高k）介电材料隔开，这也会分散载流子。传输测量到非常低的温度将使我们能够评估Ge提供的全部设备潜力。在项目结束时，我们期望对Ge表面取向、通道方向和应变全矩阵中二维载流子输运的实践和理论方面有一个全面的了解。这些知识可以用于帮助实现纳米电子学和未来自旋电子学时代所需的新一代高性能器件的巨大优势。

Germanium, in at the birth of the electronics revolution, is experiencing a renaissance as a semiconductor material - possibly even rivalling silicon, and is attracting huge interest as the silicon end-game hots up. It is perceived, audaciously but by many, as a potential candidate to maintain silicon-like technology and associated devices well beyond the envisaged end of silicon development (around 2020) and also take the technology into exciting new areas and performance regimes. This proposal sets out to explore some of the intriguing aspects and consequences of the fundamental electronic structure of Ge not previously examined. There are good theoretical arguments to suggest that some critical performance parameters can be dramatically enhanced if carriers travel in non-conventional crystallographic directions and when the germanium is under strain. We will investigate how these new environments affect the velocity/mobility and effective mass of the carriers (electrons and holes) and the processes that impede their motion (scattering).The project will be conducted by three UK university groups uniquely positioned to undertake this research and with international reputations for epitaxial growth of strained Ge (Warwick), transmission electron microscopy (TEM) for structural characterization on the nanoscale (Sheffield) and carrier transport modelling (Glasgow). The industrial standard CVD growth system at Warwick puts us in a unique position to contribute to this field of research, with good prospects of the high quality Ge structures being available early in the programme. Participation of IMEC, the leading European nano-processing laboratory, will give us unparalleled access to tools not available in the UK. Our intellectual property will be fully protected and could be exploited by numerous companies in the UK.The principal objective is to study 2D carrier transport in these largely untried orientations and to look for significant enhancements in carrier mobility compared to the conventional (100) orientation. Similar investigations are currently underway in silicon and it is opportune to now explore this in Ge. It is particularly timely in the light of IMEC's recent progress in Ge device fabrication using essentially silicon processing techniques.The programme consists of three integrated workpackages:WP1 - Growth and processing of strained Ge channel structures: Epitaxial processes will be developed, structural characterisation performed including high resolution TEM, and simple structures processed for electrical measurement.WP2 - Modulation doped buried channel structures: Initial assessment and screening of orientation and strain influences on hole and electron transport, quickly targeting optimised structures and specifically avoiding any perturbing effects of processing that may be detrimental to electron transport. Results from the measurements will be used by the Glasgow Device Modelling Group to develop/refine basic scattering and mobility models for this materials system and provide pointers to final choice of structures.WP3 - Surface-channel device structures: Structures containing a gate electrode to modulate the carrier population and make it an active device. The gate is separated from the channel by a very thin layer of a new (high-k) dielectric material, which will also scatter the carriers. Transport measurements down to very low temperatures will allow us to appraise the full device potential offered by Ge.By the end of the project we would expect to have a thorough understanding of the practical and theoretical aspects of 2D carrier transport in the full matrix of Ge surface orientations, channel directions and strain. Such knowledge can then be used to great advantage in helping realise new generations of highly performing devices that are needed in the nanoelectronics and the futuristic spintronics era.