DEVELOPMENT OF PULSED & FT ESR SPECTROMETER TIMING

这个子项目是许多利用资源的研究子项目之一 由NIH/NCRR资助的中心拨款提供。子项目的主要支持 而子项目的主要调查员可能是由其他来源提供的， 包括其它NIH来源。 列出的子项目总成本可能 代表子项目使用的中心基础设施的估计数量， 而不是由NCRR赠款提供给子项目或子项目工作人员的直接资金。 定时系统是脉冲ESR谱仪的核心部件。具有纳秒脉冲的FT-ESR谱仪需要皮秒级的脉冲稳定性和定时分辨率。只有一个高价格的模块化类型的延迟发生器模型具有这样的分辨率和适度快速的重新编程能力是商业上可用的。一个完整的系统需要几个这样的单元，系统整合所需的模块必须在内部设计。为此，我们设计并构建了一套完整的低成本系统，专为脉冲和FT-ESR光谱而量身定制。我们的努力完全符合现代趋势，即采用片上系统设计方法。我们的最新版本的定时硬件是驻留在FPGA（现场可编程门阵列），并在真实的时间与SHARC DSP的更新脉冲序列的能力，在20微秒或更快的控制。这是在停流或连续流动力学实验中所需的真实的时间中进行1D或2D采集的先决条件，其中整个实验需要几秒钟。 这需要编写特殊的DSP代码，以便使整个快速数据采集过程与主机中的平均ADC同步。关键时序硬件位于FPGA中，时钟频率为125 MHz，因此提供8 ns的时序分辨率。进一步的分辨率提高到10 ps是通过低电压ECL电路提供的8个脉冲，1个触发通道，和2行TWTA精细选通。 因此，定时系统具有11个精细定时通道。还有额外的输出通道：四条线路用于相位控制，四条线路具有8 ns分辨率，适用于TWTA粗选通等要求较低的任务。该系统是50 ps分辨率原型系统的第二次设计迭代，具有更小的外形尺寸和显著降低的功耗（系数为4），从3.3 V源汲取不到6A。

This subproject is one of many research subprojects utilizing the resources provided by a Center grant funded by NIH/NCRR. Primary support for the subproject and the subproject's principal investigator may have been provided by other sources, including other NIH sources. The Total Cost listed for the subproject likely represents the estimated amount of Center infrastructure utilized by the subproject, not direct funding provided by the NCRR grant to the subproject or subproject staff. The timing system is a central component of a pulsed ESR spectrometer. A FT-ESR spectrometer featuring nanosecond pulses requires picosecond level pulse stability and timing resolution. Only one highly-priced model of a delay generator of modular type featuring such resolution and moderately fast reprogram ability is available commercially. Several such units would be necessary for a complete system, and modules necessary for system integration would have to be designed in-house. For this reason, we designed and built a complete low-cost system, tailored for pulsed and FT-ESR spectroscopy. Our efforts are well in-line with modern trends, which follow a system-on-a-chip design approach. The latest version of our timing hardware is residing in FPGA (field-programmable gate array) and is controlled in real time with SHARC DSP with the capability of updating a pulse sequence in 20 micro s or faster. This is a prerequisite for 1D or 2D acquisition ¿in real time¿ required in stopped-flow or continuous flow kinetic experiments wherein the whole experiment takes a few seconds. This would require writing special DSP code in order to synchronize the whole process of rapid data collection with the averaging ADC, residing in the host. The critical timing hardware resides in FPGA, clocked at 125 MHz, thus providing 8 ns timing resolution. A further resolution improvement down to 10 ps is provided by means of low-voltage ECL circuitry for 8 pulses, 1 trigger channel, and 2 lines for TWTA fine gating. The timing system thus has 11 channels of fine timing. There are additional output channels: four lines for phase control and 4 lines with 8 ns resolution for less demanding tasks such as TWTA coarse gating. This system, which is the second design iteration of the 50 ps resolution prototype system, has smaller form-factor and considerably reduced power consumption (a factor of 4), drawing less than 6A from a 3.3 V source.