Efficient hardware implementations of decimal floating-point arithmetic unit

最近，许多商业应用对十进制算术运算的需求很大，包括金融分析、税务计算、电话计费、货币兑换、基于互联网的应用程序和电子商务。因此，十进制算术运算的规范最近被添加到电气和电子工程师协会(IEEE)754浮点算术标准的未经批准的草案(截至2006年10月)中。硬件中的二进制浮点运算可以处理十进制算术密集型应用，但十进制数据可以用十进制运算单元更准确地表示。由于许多十进制数不能准确地用二进制表示，因此需要以十进制格式存储数据并使用十进制算术软件处理数据。即使十进制浮点算术软件消除了转换错误，众所周知，十进制浮点软件通常比在硬件中实现的二进制浮点慢100到1000倍。因此，需要十进制浮点算术的硬件实现。本研究将研究十进制浮点运算单元的高效硬件实现。浮点硬件具有较宽的动态范围和较高的计算精度，但却占据了芯片总面积和功耗的很大比例。因此，它的使用，特别是在低功率应用中，是有限的。由于其不可接受的硬件成本，许多嵌入式微处理器不包括浮点单元。这项研究将探索一种通过最小化十进制浮点数据的位宽表示来降低十进制浮点硬件成本和功耗的方法。通过使用最小化的十进制位宽浮点单元，十进制浮点位宽减小的结果可以提供显著的硬件成本和功率节约。

Recently, there are significant demands for decimal arithmetic operations for many commercial applications, including financial analysis, tax calculation, phone billing, currency conversion, Internet based applications, and e-commerce. Consequently, specifications for decimal arithmetic operations have recently been added to the unapproved draft (as of Oct. 2006) of the Institute of Electrical and Electronics Engineers (IEEE) 754 Standard for Floating-Point Arithmetic. Binary floating-point arithmetic in hardware can handle decimal arithmetic-intensive applications, but decimal data can be more accurately represented by a decimal arithmetic unit. Since many decimal numbers cannot be exactly represented in binary, it is desirable to store data in a decimal format and process data using decimal arithmetic software. Even if decimal floating-point arithmetic software eliminates conversion errors, it is known that decimal floating-point software is typically 100 to 1,000 times slower than binary floating-point implemented in hardware. Therefore, there is need for hardware implementations of decimal floating-point arithmetic. Efficient hardware implementations of decimal floating-point arithmetic unit will be studied in this proposed research. The result of this research will improve the performance and the accuracy of many commercial applications significantly.Floating-point hardware offers a wide dynamic range and high computation precision, yet occupies large fractions of total chip area and power consumption. Therefore its usage, especially in low-power applications, is limited. Many embedded microprocessors do not include a floating-point unit due to its unacceptable hardware cost. This proposed research will explore a way of reducing decimal floating-point hardware cost and power consumption by minimizing the bit-width representation of decimal floating-point data. The result of decimal floating-point bit width-reduction can deliver a significant hardware cost and power saving through the use of a minimized decimal bit-width floating-point unit.