Memory footprint and run-time scalability for FPGA CAD algorithms

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In this project, we will investigate methods of improving the scalability of computer-aided design tools that map circuits to Field-Programmable Gate Arrays (FPGAs). Field-Programmable Gate Arrays provide a low-risk, low-cost implementation path for a wide variety of digital circuits. To map circuits to these devices, engineers employ a suite of compilation tools. These tools require significant computing resources, especially when mapping circuits to state-of-the-art FPGAs. As the capacity of FPGAs grow, the problem will become even more severe. Unless the scalability of FPGA CAD tools is addressed, the long run times and large memory footprints will become a hindrance to future FPGA scaling, leading to increased costs and design times for companies which use these devices.