Parallel simulation of digital hardware models on AMD GPUs

本研究通过利用现代多核CPU和AMD图形处理单元（GPU）提供的并行性来解决加速数字硬件系统模型仿真的挑战。特别是，研究将集中在构建技术和实现这些技术的工具上，以在多核CPU和GPU上分布寄存器传输级（RTL）模型的仿真。注意，SystemC的参考实现提供了一个不可并行化的调度器。因此，本研究将首先扩展SystemC参考实现，以允许SystemC模型的并行执行。然后，我们将开发一个编译器，它将分析SystemC RTL模型，并自动生成针对AMD GPU的OpenCL内核。为了允许SystemC进程的一个子集在多核CPU上执行，而在GPU上执行其他进程，我们将开发一种基于包装器的交叉通信技术。 我们将在MPEG编码器/解码器、JPEG编码器/解码器和Canny边缘滤波器等基准测试上对我们的技术和工具进行实验评估。

This research addresses the challenge of accelerating simulation of digital hardware system models by utilizing the parallelism offered by modern multicore CPUs and AMD graphics processing units (GPU)s. In particular, the research will focus on building techniques and a tool that implements these techniques to distribute the simulation of register-transfer level (RTL) models across both the multicore CPUs and the GPUs. Note that SystemC's reference implementation provides a non-parallelizable scheduler. Consequently, the research will first extend SystemCs reference implementation to allow for parallel execution of SystemC models. Then, we will develop a compiler that will analyze SystemC RTL models, and automatically generate OpenCL kernels targeting AMD GPUs. In order to allow for a subset of SystemC processes to execute on the multicore CPUs and others on the GPU, we will develop a wrapper-based technique for cross-communication. We will experimentally evaluate our techniques and tool on benchmarks such as MPEG encoder/decoder, JPEG encoder/decoder, and a Canny edge filter.