Synergistic Synthesis Methodologies and Computer-Aided Design Tools for Analog and RF Integrated Circuits in Advanced Technologies

90 nm及以下工艺的晶体管性能受到外部布局相关效应（LDE）的强烈影响，例如晶体管阱邻近效应和应力效应。最近的研究表明，在纳米工艺节点处忽略LDE会导致晶体管性能的15%-30%的变化，这可能容易导致模拟/RF集成电路（IC）的故障。当使用领先的商用模拟/RF设计方法时，在生成布局之前，相关的LDE对电路性能的影响是未知的。因此，在先进技术中不可避免地需要大量的设计迭代以及人工干预。

Transistor performance in the 90nm and below technologies is strongly affected by extrinsic layout-dependent effects (LDEs), such as transistor well proximity and stress effects. Recent research has shown that ignoring LDEs at nanometer process nodes can cause 15%-30% variation in the transistor performance, which may readily lead to malfunction of analog/RF integrated circuits (IC). When using leading-edge commercially available analog/RF design methodologies, the associated LDE impact on circuit performance is unknown before the layout is generated. Thus, a large number of design iterations as well as manual intervention are inevitably required in advanced technologies.