Automatic FPGA Interconnect Synthesis and Understanding FPGA Architecture

近年来，技术进步的快速步伐是由制造具有不断增加的能力的数字芯片的能力驱动的。每一代新的芯片制造技术都使用更小的晶体管，并在计算能力方面提供指数级的改进。不太为人所知的是，设计和制造这些芯片所需的复杂性和投资也在以接近指数的速度增长，威胁着未来的进步。幸运的是，预制的用户可编程芯片（称为现场可编程门阵列（FPGA））的兴起，使得使用这种奇妙的技术成为可能，其风险和复杂性要小得多。事实上，绝大多数数字硬件设计工作都是使用FPGA完成的;只有在非常高容量的系统（例如计算机和移动的设备）中才会使用定制芯片。在其他地方，使用某种形式的可编程设备-某种计算机处理器或FPGA。在这项研究中，我们要解决的FPGA的广泛使用和采用有两个关键障碍：首先，预制的基于FPGA的硬件的优势必须与另一种预制但可编程的数字芯片进行比较：计算机，它是用软件编程的。开发软件比开发硬件容易得多，而且有更多的人有能力编写软件。长期以来，研究和工业界一直在努力使硬件的创建变得更容易，但这些努力中的许多努力都是为了结果的质量。然而，硬件的性能和能效是其相对于在处理器上运行的软件的关键优势。我们在这项研究中的目标是找到其他方法，使硬件设计过程更容易，而不会失去结果的质量。在设计过程中最困难的事情之一是硬件计算单元之间的互连设计。每一个这样的链接必须建立适当的计算的性能需求。我们建议建立，分阶段，一个工具，帮助设计师更自动地创建和不同的互连面对特定的性能要求。我们的最终目标是自动优化互连设计，从而释放设计人员的负担，重新实现它多次。有了这个功能，我们相信它将使设计师的工作更容易，并使高级工具能够更成功地帮助设计过程的其他部分。更广泛采用FPGA的第二个障碍是使预制器件有效可编程所需的灵活性成本。在大批量应用中，成本可能高得令人望而却步：简单的可编程逻辑的成本是不可编程逻辑的十到三十倍，正如我们小组在一篇被广泛引用的论文中所报道的那样。该研究提案的第二个重点是探索一种将电路合成为FPGA的全新方法，以更深入地了解实际所需的最小灵活性。我们计划通过构建一种综合方法来实现这一点，该方法将许多先前分离的步骤结合起来，这些步骤用于将工程师的设计放入FPGA中。与此同时，我们将谨慎地改变现有的灵活性，减少现有的灵活性。我们的目标是深入了解如何降低灵活性，从而降低成本。最后，我们的研究小组以唯一的FPGA开源综合工具链而闻名，该工具链在全球范围内用于FPGA架构和CAD研究以及初创公司。我们计划继续改进该软件的功能和复杂性。

The fast pace of technological advancement in recent years has been driven by the ability to fabricate digital chips with ever-increasing capability. Each new generation of chip fabrication technology uses smaller transistors and provides exponential improvements in computing capacity. It is less well known that the sophistication and investment required to design and build those chips has *also* been increasing at a near-exponential rate, threatening this progress in the future. Fortunately, the rise of pre-fabricated, user-programmable chips, known as Field-Programmable Gate Arrays (FPGAs), make it possible to use this fantastic technology with far less risk and sophistication. Indeed, the vast majority of all digital hardware design work is done using FPGAs; only in the very high volume systems (such as those in computers and mobile devices) are custom-built chips are used. Everywhere else, some form of programmable device is used - either a computer processor of some kind or an FPGA. There are two key barriers to the wider use and adoption of FPGAs that we address in this research: First, advantages of pre-fabricated FPGA-based hardware must be compared to the other kind of pre-fabricated but programmable digital chips: computers, which are programmed with software. It is much easier to create software than hardware and there many more people capable of writing software. There has long been an effort in research and industry to make the creation of hardware easier, but many of these efforts trade that ease for quality of result. However, it is that performance and energy-efficiency of hardware that are its key advantages over software running on processor. Our goal in this research is to find other ways of making the hardware design process easier, without losing the quality of the result. One of the hardest things to do in the design process is the design of interconnection between hardware computational units. Each such link must be built appropriate to the performance needs of the computation. We propose to build, in stages, a tool that helps the designer more automatically create and vary that interconnect in the face of specific performance requirements. Our ultimate goal is to automatically optimize the interconnect design, and thus release the designer from the burden of re-implementing it many times. With this capability, we believe it will make the designer's job much easier, and enable high-level tools to more successfully help with other parts of the design process. The second barrier to the wider adoption of FPGAs is the cost of the flexibility required to make a pre-fabricated device usefully programmable. The cost can be prohibitive in high volume applications: simple programmable logic is ten to thirty times the cost of non-programmable logic, as our group has reported in a widely-cited paper. The second thrust of this research proposal is to explore a fundamentally new way of synthesizing circuits into FPGAs, as a way to more deeply understand the minimum amount of flexibility actually required. We plan to do this by building a synthesis approach that combines many of the previously-separated steps that are used to take an engineer's design and put it into the FPGA. At the same time, we will carefully vary the amount of flexibility available, reducing it from its current amount. Our goal is to gain insight into ways to reduce flexibility and therefore cost. Finally, our research group is well-known for the only open-source synthesis tool chain for FPGAs, used throughout the world in FPGA architecture and CAD research and startups. We plan to continue to improve the capabilities and sophistication of this software.