Synergistic Synthesis Methodologies and Computer-Aided Design Tools for Analog and RF Integrated Circuits in Advanced Technologies

晶体管在90 nm及以下工艺中的性能受到外部版图相关效应(LDE)的强烈影响，例如晶体管的完好性和应力效应。最近的研究表明，忽略纳米工艺节点上的LDE会导致晶体管性能变化15%-30%，这很容易导致模拟/射频集成电路(IC)的故障。当使用先进的商用模拟/射频设计方法时，在生成布局之前，相关的LDE对电路性能的影响是未知的。因此，在先进的技术中，不可避免地需要大量的设计迭代以及人工干预。 在这项研究计划中，将研究协同综合方法和计算机辅助设计工具，使性能优化和物理效果相融合。提出了一种基于LDE和变化感知的电路拓扑综合方法，该方法可以通过考虑相关的版图影响来有效地主动探索搜索空间。研究了一种新颖的两阶段LDE、变化和寄生感知电路尺寸调整方法，该方法首先采用基于符号方程的快速全局优化方案，然后采用基于仿真的精细尺寸调整方法。我们还将研究自动版图合成策略，以解决与LDE、变异和寄生相关的约束。 由于对复杂的模拟效应高度敏感，模拟/射频集成电路已被认为是迅速将混合信号系统芯片产品推向市场的设计瓶颈。感知LDE的模拟/射频IC综合中的系统对策尚未在全球范围内得到解决。这一研究计划具有巨大的商业化潜力，解决了纳米技术中模拟/射频IC综合中日益具有挑战性的LDE问题及其深刻的交互性质。该计划将通过显著提高设计生产率和可靠性，使模拟/射频设计界受益，并将增强加拿大在该领域的竞争优势。

Transistor performance in the 90nm and below technologies is strongly affected by extrinsic layout-dependent effects (LDEs), such as transistor well proximity and stress effects. Recent research has shown that ignoring LDEs at nanometer process nodes can cause 15%-30% variation in the transistor performance, which may readily lead to malfunction of analog/RF integrated circuits (IC). When using leading-edge commercially available analog/RF design methodologies, the associated LDE impact on circuit performance is unknown before the layout is generated. Thus, a large number of design iterations as well as manual intervention are inevitably required in advanced technologies. In this research program, synergistic synthesis methodologies and computer-aided design tools will be studied to make a fusion between performance optimization and physical effects. An LDE- and variation-aware circuit topology synthesis methodology, which can effectively explore the search space proactively by considering associated layout impact, will be developed. A novel two-stage LDE-, variation- and parasitic-aware circuit- sizing methodology, which first deploys a symbolic-equation-based scheme for quick global optimization and then a simulation-based method for refined sizing, will be studied. We will also investigate automatic layout synthesis strategies to address LDE-, variation- and parasitic-related constraints. Analog/RF ICs have been recognized as the design bottleneck for promptly pushing mixed-signal system-on- chip products to market due to high sensitivity to the complicated analog effects. Systematic countermeasures in the LDE-aware synthesis of analog/RF ICs have not yet been addressed worldwide. With enormous potential for commercialization, this proposed research program addresses the increasingly challenging LDE problems and their profound interactive nature that cannot be ignored for analog/RF IC synthesis in nanometer technolo- gies. This program will benefit the analog/RF design community through significant improvements in design productivity and reliability, and will enhance Canada's competitive advantage in this field.