An Intelligent, Parallel Framework for Field-Programmable Gate-Array Placement and Routing

自1984年左右问世以来，现场可编程门阵列(现场可编程门阵列)的使用量有了巨大的增长，因为它们可以极大地减少原型电路和小批量产品的设计周转时间和制造成本。这是由于可重新配置的逻辑块、宏块和可编程互连在一个FPGA上的可用性。据估计，到2016年，全球的现场可编程门阵列市场将达到100亿美元，其中通信、汽车、医疗、计算机存储、军事和无线都是重要的终端市场。然而，随着现代现场可编程门阵列中特征尺寸的不断缩小和器件容量的不断增加，设计自动化行业面临着一个老问题：布局和布线所花费的时间仍然主导着FPGA编译过程。虽然目前的布局和布线工具可以产生高质量的解决方案，但对于最大的设计来说，编译时间可能在几个小时甚至几天的量级上。长时间运行不仅会对工程生产率和成本产生不利影响，还会严重阻碍习惯于编译时间为几秒或几分钟的软件开发人员采用现场可编程门阵列。 该研究方案的主要目标是开发一种智能的并行框架，通过更高效和智能地执行布局和布线，帮助设计者减少编译FPGA电路所花费的时间。该方案的创新之处在于将最先进的机器学习和数据挖掘技术与运行在多核和多核并行体系结构上的创新的并行布局和布线方法相结合。该框架的一个关键特征是能够从过去的布局和布线问题中学习，以更有效和高效地解决未来的布局和布线问题。 这项工作的总体意义将是为加拿大工业提供可扩展的、并行的FPGA布局和布线工具，这些工具可以产生高质量的解决方案，同时避免过长的编译时间。由此产生的工具将有助于减少设计周期时间，从而减少设计成本。设计时间和设计成本都是基于现场可编程门阵列的电子产品制造企业非常重要的考虑因素。

Since their inception circa 1984, Field Programmable Gate Arrays (FPGAs) have seen an enormous growth in usage because they can dramatically reduce design turn-around time and manufacturing costs for prototype circuits and small to high-volume products. This is made possible by the availability of reconfigurable logic blocks, macro blocks, and programmable interconnections on a FPGA. It has been estimated that the world-wide FPGA market will reach $10 billion by 2016, with communication, automotive, medical, computer storage, military and wireless all important end markets. However, as the feature size continues to shrink and device capacity continues to increase in modern FPGAs, the design-automation industry is facing an old problem: the time spent for placement and routing is still dominating the FPGA compilation process. While current placement and routing tools produce quality solutions, compile times can be on the order of hours or even days for the largest designs. Long run times not only adversely impact engineering productivity and costs, they act as a serious impediment to the adoption of FPGAs by software developers who are used to compilation times of seconds or minutes. The primary goal of this research proposal is to develop an intelligent, parallel framework that can help a designer reduce the amount of time spent compiling circuits for FPGAs by performing placement and routing more efficiently and intelligently. The novelty of this proposal lies in combining state-of-the-art machine-learning and data-mining techniques with innovative parallel placement and routing methods running on multicore and many-core parallel architectures. A key feature of the proposed framework is its ability to learn from past placement and routing problems to more effectively and efficiently solve future placement and routing problems. The overall significance of this work will be to provide Canadian industry with scalable, parallel FPGA placement and routing tools that can produce high-quality solutions, while avoiding excessively long compile times. The resulting tools will help reduce the design cycle time and, consequently, design cost. Both design time and design cost are very important considerations for companies manufacturing electronic products based on FPGAs.