Automatic FPGA Interconnect Synthesis and Understanding FPGA Architecture

近年来技术进步的快速步伐是由制造能力不断增强的数字芯片的能力推动的。每一代新的芯片制造技术都使用更小的晶体管，并在计算能力方面提供指数级的改进。不太为人所知的是，设计和制造这些芯片所需的尖端技术和投资也一直在以接近指数的速度增长，威胁着未来的这种进步。幸运的是，被称为现场可编程门阵列(现场可编程门阵列)的预制、用户可编程芯片的兴起，使得以低得多的风险和复杂性使用这种奇妙的技术成为可能。事实上，绝大多数数字硬件设计工作都是使用现场可编程门阵列完成的；只有在非常大量的系统中(如计算机和移动设备中的系统)才使用定制的芯片。在其他任何地方，都会使用某种形式的可编程设备--某种类型的计算机处理器或FPGA。**我们在这项研究中解决的FPGA的更广泛使用和采用存在两个关键障碍：第一，基于预制FPGA的硬件的优势必须与另一种预制但可编程的数字芯片进行比较：计算机，它是用软件编程的。创建软件比创建硬件容易得多，而且有能力编写软件的人要多得多。长期以来，研究和工业领域一直在努力让硬件的创建变得更容易，但其中许多努力都是为了换取结果的质量。然而，与运行在处理器上软件相比，硬件的性能和能效才是其主要优势。我们在这项研究中的目标是找到其他方法来简化硬件设计过程，而不会损失结果的质量。在设计过程中最难做的事情之一是硬件计算单元之间的互连设计。每个这样的链接都必须构建成适合计算的性能需求。我们建议分阶段构建一个工具，帮助设计者在面对特定性能要求时更自动地创建和更改互连。我们的最终目标是自动优化互连设计，从而将设计者从多次重新实现的负担中解脱出来。有了这一能力，我们相信它将使设计者的工作变得容易得多，并使高级工具能够更成功地帮助设计过程的其他部分。**广泛采用现场可编程门阵列的第二个障碍是使预制设备有效编程所需的灵活性成本。在大容量应用中，成本可能会高得令人望而却步：正如我们小组在一篇被广泛引用的论文中所报告的那样，简单的可编程逻辑的成本是非可编程逻辑的十到三十倍。这项研究提案的第二个重点是探索一种将电路合成到现场可编程门阵列中的根本新方法，以此来更深入地理解实际所需的最低灵活性。我们计划通过构建一种综合方法来实现这一点，该方法结合了许多以前分离的步骤，这些步骤用于将工程师的设计放入FPGA中。与此同时，我们将谨慎地改变可用灵活性的数量，将其从目前的数量减少。我们的目标是深入了解如何降低灵活性，从而降低成本。**最后，我们的研究小组以唯一的开源综合工具链而闻名，该工具链用于全球范围内的FPGA架构、CAD研究和初创企业。我们计划继续改进这款软件的功能和完善程度。

The fast pace of technological advancement in recent years has been driven by the ability to fabricate digital chips with ever-increasing capability. Each new generation of chip fabrication technology uses smaller transistors and provides exponential improvements in computing capacity. It is less well known that the sophistication and investment required to design and build those chips has *also* been increasing at a near-exponential rate, threatening this progress in the future. Fortunately, the rise of pre-fabricated, user-programmable chips, known as Field-Programmable Gate Arrays (FPGAs), make it possible to use this fantastic technology with far less risk and sophistication. Indeed, the vast majority of all digital hardware design work is done using FPGAs; only in the very high volume systems (such as those in computers and mobile devices) are custom-built chips are used. Everywhere else, some form of programmable device is used - either a computer processor of some kind or an FPGA.**There are two key barriers to the wider use and adoption of FPGAs that we address in this research: First, advantages of pre-fabricated FPGA-based hardware must be compared to the other kind of pre-fabricated but programmable digital chips: computers, which are programmed with software. It is much easier to create software than hardware and there many more people capable of writing software. There has long been an effort in research and industry to make the creation of hardware easier, but many of these efforts trade that ease for quality of result. However, it is that performance and energy-efficiency of hardware that are its key advantages over software running on processor. Our goal in this research is to find other ways of making the hardware design process easier, without losing the quality of the result. One of the hardest things to do in the design process is the design of interconnection between hardware computational units. Each such link must be built appropriate to the performance needs of the computation. We propose to build, in stages, a tool that helps the designer more automatically create and vary that interconnect in the face of specific performance requirements. Our ultimate goal is to automatically optimize the interconnect design, and thus release the designer from the burden of re-implementing it many times. With this capability, we believe it will make the designer's job much easier, and enable high-level tools to more successfully help with other parts of the design process.**The second barrier to the wider adoption of FPGAs is the cost of the flexibility required to make a pre-fabricated device usefully programmable. The cost can be prohibitive in high volume applications: simple programmable logic is ten to thirty times the cost of non-programmable logic, as our group has reported in a widely-cited paper. The second thrust of this research proposal is to explore a fundamentally new way of synthesizing circuits into FPGAs, as a way to more deeply understand the minimum amount of flexibility actually required. We plan to do this by building a synthesis approach that combines many of the previously-separated steps that are used to take an engineer's design and put it into the FPGA. At the same time, we will carefully vary the amount of flexibility available, reducing it from its current amount. Our goal is to gain insight into ways to reduce flexibility and therefore cost.**Finally, our research group is well-known for the only open-source synthesis tool chain for FPGAs, used throughout the world in FPGA architecture and CAD research and startups. We plan to continue to improve the capabilities and sophistication of this software.