Physical vapour deposition of ferroelectric and multiferroic tunnel junctions

铁电隧道结（ftj）是集成计算机电路中取代闪存的最强竞争者，因为它们结合了低成本、非易失性、占地面积小、快速读写周期、低能耗、非破坏性读出以及最近的cmos兼容性。工作原理是基于两种导电状态之间的电阻切换，在ftj的情况下，这种状态是通过不同的自发极化状态提供的。本质上只有几个单元格厚，它们也适合集成在交叉棒阵列中，以结合内存和逻辑的特性，从而实现创新的电路架构，在处理器运行期间具有巨大的节能潜力。我们最近展示了具有经过验证的CMOS兼容性的ftj，仅使用已经成为CMOS加工一部分的材料HfZrO2，并将所有工艺参数，特别是沉积温度保持在公差范围内。随着与工业合作伙伴合作提交专利的概念验证，这些电子功能的进一步发展依赖于射频磁控溅射工艺参数的优化，这是一种从实验室到制造规模都很容易采用的工艺。另一方面，需要排除寄生开关效应，如丝介导的电阻开关，并必须确定最常见的故障机制，如点缺陷。为此，我们与加拿大光源的电子显微镜和光谱（PEEM）光束线合作，加拿大光源是加拿大最先进的纳米级化学和结构成像基础设施。为了确定这些电子瓦片在给定规格（主要是导通和关断状态之间的电阻比）下的全部潜力，我们与NSERC/IBM加拿大工业研究主席合作，指导集成到最有前途的电路架构。此次合作的主要目标是为新型非易失性存储器开发一种工业大型机兼容工艺，以在写入速度，能耗和耐用性方面优于闪存。****

Ferroelectric tunnel junctions (FTJs) are the strongest contender to replace flash memory in integrated computer circuitry as they combine low-cost, non-volatility, small footprint, fast read- write cycles, low energy consumption, non-destructive readout and, since very recently, cmos-compatibility. The principle of operation is based on resistive switching between two conductive states that, in the case of FTJs are provided through the distinct state of spontaneous polarization. Intrinsically only a few unit cells thick, they are also suited for integration in crossbar arrays to combine features of memory and logic thus enabling innovative circuit architectures with tremendous potential for energy savings during processor operation. We have very recently demonstrated FTJs with proven CMOS compatibility, using only materials, HfZrO2, that are already part of cmos processing and keeping all process parameters, in particular the deposition temperature, within tolerances. With the proof of concept submitted for patent in collaboration with the industrial partner, the further development of these electronic functions relies for one on the optimization of process parameters for RF magnetron sputtering, a process to be readily adopted from laboratory to fabrication scale. For the other, parasitic switching effects, such as filamentary-mediated resistive switching need to be excluded and the most common failure mechanisms, e.g. point defects, will have to be identified. For this purpose, we collaborate with the electron microscopy and spectroscopy (PEEM) beam line at the Canadian Light Source, Canada's most advanced infrastructure for nanoscale chemical and structural imaging. In order to determine the full potential of these electronic tiles for given specifications (mainly the resistance ratio between on and off state), we collaborate with the NSERC/IBM Canadian industrial research chair to guide the integration towards the most promising circuit architecture. The main objective of this partnership is to develop an industrial main-frame compatible process for a novel non-volatile memory generation to outperform flash in terms of write speed, energy consumption and endurance.****