EIA: Rapid Thermal Vapor Phase Epitaxy

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The objective of this project is to demonstrate that standard vapor phase epitaxial growth techniques can be extended into time/temperature regimes to allow fabrication of sub 100 A layers with abrupt and/or quasi abrupt interfaces, with fewer defects and at much lower cost than with MBE. The material to be used for this study will be silicon, due to the high growth rates of silicon VPE, the difficulty of silicon MBE, and the lack of any alternate growth technique. Wafers will be heated rapidly while in a gas flow using DC arc and flash lamps. Cooling will be done using direct contact with a "cool" plate. Two growth chemistries will be explored: pyrolysis of silane which can be done at temperatures close to 800 C for very abrupt junction formation, and reduction of chlorosilanes for the highest quality material and potentially, completely selective growth. Films will be characterized chemically, electrically, and microscopically. As final proof of material quality transistors will be fabricated and characterized with attention being paid to a ballistic bipolar device.