Propagation Delays in the Bilevel and Trilevel Multilayer High Density Interconnections on the GaAs Based VHSIC

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There is an increasing demand for circuits with higher speeds and higher component densities. This requires millions of closely spaced interconnection lines that integrate the components on a chip. Parasitic capacitances associated with the interconnections in such high density environments have become the primary factors in the evolution of the VHSIC technology. Particularly for the development of the ASIC's (application specific integrated circuits), it is important to know the propagation delays expected in an IC (integrated circuit) before its fabrication is undertaken. Objectives of the proposed research are: (a) development of reliable models for the parasitic capacitances associated with the multilevel and multilayer interconnection in the high-density environments, suitable for the GaAs-based VLSI circuits; (b) development of accurate models for the determination of the propagation delays in the multilevel and multilayer interconnections on the GaAs-based very high speed integrated circuits; (c) study of the crosstalk in the interconnections on the GaAs-based very high speed integrated circuits; and (d) fabrication of the interconnection lines on the GaAs substrate and experimental verification of the dependence of the propagation delays on the interconnect dimensions, interconnect material resistivity and other geometrical factors. This research is expected to provide a better understanding of the interactions between interconnection lines on VLSI chips as the dimensions decrease and the density of the interconnections on a chip increase. This is very important to the continued development of VLSI technology.