SGER: On Solving the 'Interconnect Problem' for the Nanotechnology Circuit Design

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This research explores the interconnect problem in nanotechnology, which involves solving problems relating to design of high density of devices and high speed of transmission of within the circuit. The approach is to investigate a modified version of the traditional metallic interconnects. The modification consists in using the concept of parallel processing by providing two or more paths between the driver and the load stacked vertically isolated from one another by insulating layers between them. In addition to heating problems, this research also studies the parasitics associated with such a structure, the propagation delays expected in it and the potential problem of crosstalk among the various paths of the same interconnect and that among the neighboring interconnects. The model of the multipath interconnects includes the self and coupling parasitic capacitances and inductances in addition to the very high-frequency effects.