SGER: On Solving the 'Interconnect Problem' for the Nanotechnology Circuit Design

本研究探讨奈米科技中的内连线问题，其中包含解决高密度元件设计与电路内高速传输的相关问题。该方法是调查传统的金属互连的修改版本。修改在于通过在驱动器和负载之间提供两个或更多个路径来使用并行处理的概念，所述两个或更多个路径通过它们之间的绝缘层而彼此垂直地隔离地堆叠。除了加热问题，本研究还研究了与这种结构相关的寄生效应，预期在它的传播延迟和潜在的串扰问题之间的各种路径的同一互连和相邻的互连。多路径互连线的模型除了考虑甚高频效应外，还考虑了自耦合寄生电容和电感。

This research explores the interconnect problem in nanotechnology, which involves solving problems relating to design of high density of devices and high speed of transmission of within the circuit. The approach is to investigate a modified version of the traditional metallic interconnects. The modification consists in using the concept of parallel processing by providing two or more paths between the driver and the load stacked vertically isolated from one another by insulating layers between them. In addition to heating problems, this research also studies the parasitics associated with such a structure, the propagation delays expected in it and the potential problem of crosstalk among the various paths of the same interconnect and that among the neighboring interconnects. The model of the multipath interconnects includes the self and coupling parasitic capacitances and inductances in addition to the very high-frequency effects.