Research Initiation: Interconnect Delay and Clock Skew Optimization in VLSI Circuits

Ciesielski博士正在研究优化信号 VLSI电路中的路径延迟和时钟偏移，目的是 提高VLSI芯片性能。 具体来说，这一目标 研究的目的是找到有效的技术， 调谐，布线延迟在超大规模集成电路芯片的最低水平， 物理设计 这将通过分配 导电层互连导线和放置接触 （通孔）层的变化。 最小化的模型 关键路径延迟的建议，其中精确RC 考虑到互连线和通孔的特性， 帐户. 这一模式将得到扩展， 互连延迟优化中的目标，例如 最小化时钟偏移，均衡数据路径延迟， 在数据路径中引入精确控制的线延迟。

Dr. Ciesielski is investigating methods for optimizing signal path delays and clock skew in VLSI circuits, with the aim of improving VLSI chip performance. Specifically, the goal of this research is to find efficient techniques for adjusting, or fine tuning, wiring delays in VLSI chips at the lowest level of physical design. This will be accomplished by assigning conducting layers to interconnect wires and placing contacts (vias) at layer changes. A model for the minimization of critical path delays is proposed, in which precise RC characteristics of interconnect wires and vias are taken into account. This model will be extended to incorporate other objectives in the optimization of interconnect delay, such as the minimization of clock skew, equalization of data path delays and introduction of precisely controlled wire delays in data paths.