Research Initiation: Interconnect Delay and Clock Skew Optimization in VLSI Circuits

Ciesielski博士正在研究优化超大规模集成电路中的信号路径延迟和时钟偏差的方法，旨在提高超大规模集成电路芯片的性能。具体来说，这项研究的目标是在最低的物理设计水平上找到有效的技术来调整或微调VLSI芯片的布线延迟。这将通过分配导电层来互连电线并在层变化处放置触点（过孔）来实现。提出了一种考虑互连导线和过孔精确RC特性的临界路径延迟最小化模型。该模型将被扩展，以纳入互连延迟优化中的其他目标，例如时钟倾斜最小化，数据路径延迟均衡以及在数据路径中引入精确控制的线延迟。

Dr. Ciesielski is investigating methods for optimizing signal path delays and clock skew in VLSI circuits, with the aim of improving VLSI chip performance. Specifically, the goal of this research is to find efficient techniques for adjusting, or fine tuning, wiring delays in VLSI chips at the lowest level of physical design. This will be accomplished by assigning conducting layers to interconnect wires and placing contacts (vias) at layer changes. A model for the minimization of critical path delays is proposed, in which precise RC characteristics of interconnect wires and vias are taken into account. This model will be extended to incorporate other objectives in the optimization of interconnect delay, such as the minimization of clock skew, equalization of data path delays and introduction of precisely controlled wire delays in data paths.