An Optoelectronic Integrated Circuit (OEIC) Galium Arsenide Receiver on a Silicon Substrate

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Development of a fully monolithic integrated receiver chip for the 1.3 and 1.55 micron fibre optic wavelengths is proposed. The chip will be fabricated on a Si substrate so that conventional bipolar MOSFET technology can be used to construct all of the preamplifier electronics. We will use an innovative method for the growth of high-quality InP and related compound epitaxial layers on silicon substrates. The hydride VPE technique would be used to compositionally grade In(x)Ga(1-x)As films on a commercially purchased GaAs/Si substrate from x = 0 to x = 0.53. InP or InGaAs(P) would then be directly deposited onto the lattice- matched In(53)Ga(47)As. Performance goals of the OEIC include a 500 Mb/s data rate, -40 dBm sensitivity and efficient light detection out to 1.65 micron. During Phase I, 75 micron planar InGaAs photodiodes, grown on GaAs/Si substrates, will be fabricated, lifetested and delivered as prototypes along with an epitaxial layer of InP grown on a silicon substrate. In Phase II, these detectors will be combined on a single chip with a Si bipolar preamplifier, thus resulting in a monolithic integrated receiver. Detector and receiver design and characterization will be done in conjunction with Prof. S.R. Forrest in the Department of Electro Physics at the University of Southern California.