An Optoelectronic Integrated Circuit (OEIC) Galium Arsenide Receiver on a Silicon Substrate

提出了一种适用于1.3微米和1.55微米光纤波长的全单片集成接收芯片。该芯片将在硅衬底上制造，因此传统的双极MOSFET技术可以用于构建所有的前置放大器电子器件。我们将使用一种创新的方法在硅衬底上生长高质量的InP和相关的化合物外延层。氢化物VPE技术将用于在商业购买的GaAs/Si衬底上对从x = 0到x = 0.53的In(x)Ga(1-x)As薄膜进行成分分级。InP或InGaAs(P)将直接沉积在晶格匹配的In(53)Ga(47)As上。OEIC的性能目标包括500mb /s的数据速率，-40 dBm的灵敏度和1.65微米的有效光检测。在第一阶段，在GaAs/Si衬底上生长的75微米平面InGaAs光电二极管将被制造、寿命测试并作为原型与在硅衬底上生长的InP外延层一起交付。在第二阶段，这些探测器将与一个硅双极前置放大器组合在一个芯片上，从而形成一个单片集成接收器。探测器和接收器的设计和特性将与南加州大学电物理系的S.R. Forrest教授一起完成。

Development of a fully monolithic integrated receiver chip for the 1.3 and 1.55 micron fibre optic wavelengths is proposed. The chip will be fabricated on a Si substrate so that conventional bipolar MOSFET technology can be used to construct all of the preamplifier electronics. We will use an innovative method for the growth of high-quality InP and related compound epitaxial layers on silicon substrates. The hydride VPE technique would be used to compositionally grade In(x)Ga(1-x)As films on a commercially purchased GaAs/Si substrate from x = 0 to x = 0.53. InP or InGaAs(P) would then be directly deposited onto the lattice- matched In(53)Ga(47)As. Performance goals of the OEIC include a 500 Mb/s data rate, -40 dBm sensitivity and efficient light detection out to 1.65 micron. During Phase I, 75 micron planar InGaAs photodiodes, grown on GaAs/Si substrates, will be fabricated, lifetested and delivered as prototypes along with an epitaxial layer of InP grown on a silicon substrate. In Phase II, these detectors will be combined on a single chip with a Si bipolar preamplifier, thus resulting in a monolithic integrated receiver. Detector and receiver design and characterization will be done in conjunction with Prof. S.R. Forrest in the Department of Electro Physics at the University of Southern California.