RIA: VLSI CORDIC Parallel Processor Architectures for the Singular Value Decomposition

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The objectives of this research are a) to develop Coordinate Rotation Algorithms (CORDIC) using complex arithmetic; b) to develop a fault tolerant Singular Value Decomposition (SVD) array architecture; and c) to develop the VLSI implementation of a fixed-point CORDIC SVD processor-array element. The principal investigator has previously shown the applicability of high-speed computer arithmetic algorithms, which includes the mapping of CORDIC to the SVD of real matrix. Based on the CORDIC data path chips designed, fully custom CMOS chips are being fabricated through the MOSIS service. The data path designs are then combined to yield a complete array-element chip and configured into a prototype array. Improvements to numerical algorithms will lead to a CORDIC SVD processor using complex arithmetic. Recent advances in VLSI have encouraged the development of special- purpose processor arrays to solve computation-intensive numerical algorithms. SVD is an important matrix computational method for real- time signal processing and image processing. The results developed here will result in a custom, low-cost, reconfigurable, high-speed VLSI SVD array, which will allow many applications to be solvable in real time.