Study on Implementation and Evaluation of High-performance Asynchronous Microprocessor

采用3层金属、0.5微米规则CMOS标准单元工艺，在12.5mm × 12.5mm的空间内集成了496，367个MOS晶体管和8.6K字节的存储器宏，实现了一个32位异步微处理器。该处理器芯片在其电源电压从1.5V到6.0V的范围内变化并且其封装表面的温度通过吹风机加热到约85摄氏度并用液氮冷却的情况下正常工作，并且使用Dhetrone V2.1基准测试实现52 VAX MIPS，在室温下3.3 V时功耗为2W。该设计的一个显著特点是引入了一个新的延迟模型，称为可扩展延迟不敏感（SDI）模型，它提供了一个合理的方法，可靠和高性能的异步VLSI系统设计。该处理器已被证明实现的延迟不敏感性和高性能表明，异步事件驱动方法对于具有未来器件技术的高精度VLSI系统设计是非常有前途和令人鼓舞的。

A 32-bit asynchronous microprocessor, whose architecture was borrowed from the MIPS R2000 processor, has been fabricated using 3 layr metal, 0.5 micron rule CMOS standard cell technology, integrating 496,367 MOS transistors and 8.6K Byte memory macro in 12.5 mm x 12.5mm. The processor chip works correctly with its power supply voltage being varied through the range from 1.5V to 6.0V and the temperature of its package surface being heated up to about 85 degrees Celsius by hair dryer and cooled down with liquid nitrogen, and achieves 52 VAX MIPS using the Dhrystone V2.1 benchmark with a power consumption of 2W at 3.3 V for room temperature. A significant feature of the design is the introduction of a new delay model, called the Scalable-Delay-Insensitive (SDI) model, which provides with a reasonable approach to dependable and high-performance asynchronous VLSI system design. the delay-insensitivity and the high-performance that the processor has been proved to achieve demonstrate that the asynchronous event-driven approach is very promising and encouraging for high-preformance VLSI system design with future device technologies.